Lines Matching +full:hw +full:- +full:settle +full:- +full:time
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
24 struct clk_hw hw; member
36 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
52 static long samsung_pll_round_rate(struct clk_hw *hw, in samsung_pll_round_rate() argument
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate()
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
60 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
66 return rate_table[i - 1].rate; in samsung_pll_round_rate()
93 * Exynos SoC variants. Single register read time was usually in range in samsung_pll_lock_wait()
98 while (i-- > 0) { in samsung_pll_lock_wait()
99 if (readl_relaxed(pll->con_reg) & reg_mask) in samsung_pll_lock_wait()
104 ret = -ETIMEDOUT; in samsung_pll_lock_wait()
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, in samsung_pll_lock_wait()
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
116 static int samsung_pll3xxx_enable(struct clk_hw *hw) in samsung_pll3xxx_enable() argument
118 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable()
121 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
122 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
123 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll3xxx_enable()
128 static void samsung_pll3xxx_disable(struct clk_hw *hw) in samsung_pll3xxx_disable() argument
130 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable()
133 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
134 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
135 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
149 static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, in samsung_pll2126_recalc_rate() argument
152 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate()
156 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
182 static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, in samsung_pll3000_recalc_rate() argument
185 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate()
189 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
207 /* Maximum lock time can be 270 * PDIV cycles */
219 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, in samsung_pll35xx_recalc_rate() argument
222 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate()
226 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
245 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
248 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll35xx_set_rate() argument
251 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate()
259 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate()
260 return -EINVAL; in samsung_pll35xx_set_rate()
263 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
268 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
269 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
274 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
275 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
276 pll->lock_reg); in samsung_pll35xx_set_rate()
282 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | in samsung_pll35xx_set_rate()
283 (rate->pdiv << PLL35XX_PDIV_SHIFT) | in samsung_pll35xx_set_rate()
284 (rate->sdiv << PLL35XX_SDIV_SHIFT); in samsung_pll35xx_set_rate()
285 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
288 if (tmp & BIT(pll->enable_offs)) in samsung_pll35xx_set_rate()
289 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll35xx_set_rate()
309 /* Maximum lock time can be 3000 * PDIV cycles */
323 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, in samsung_pll36xx_recalc_rate() argument
326 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate()
331 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
332 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
354 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in samsung_pll36xx_mpk_change()
355 rate->kdiv != old_kdiv); in samsung_pll36xx_mpk_change()
358 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll36xx_set_rate() argument
361 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate()
368 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate()
369 return -EINVAL; in samsung_pll36xx_set_rate()
372 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
373 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
378 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
379 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
384 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
385 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
391 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | in samsung_pll36xx_set_rate()
392 (rate->pdiv << PLL36XX_PDIV_SHIFT) | in samsung_pll36xx_set_rate()
393 (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
394 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
397 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; in samsung_pll36xx_set_rate()
398 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
400 if (pll_con0 & BIT(pll->enable_offs)) in samsung_pll36xx_set_rate()
401 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll36xx_set_rate()
436 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, in samsung_pll45xx_recalc_rate() argument
439 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate()
443 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
448 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
449 sdiv = sdiv - 1; in samsung_pll45xx_recalc_rate()
466 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll45xx_mp_change()
467 || old_afc != rate->afc); in samsung_pll45xx_mp_change()
470 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll45xx_set_rate() argument
473 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate()
481 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
482 return -EINVAL; in samsung_pll45xx_set_rate()
485 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
486 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
491 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
492 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
501 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
502 (rate->pdiv << PLL45XX_PDIV_SHIFT) | in samsung_pll45xx_set_rate()
503 (rate->sdiv << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
506 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
508 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
510 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
511 switch (pll->type) { in samsung_pll45xx_set_rate()
513 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
516 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
523 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
524 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
569 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, in samsung_pll46xx_recalc_rate() argument
572 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate()
576 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
577 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
578 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
582 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
585 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
603 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll46xx_mpk_change()
604 || old_kdiv != rate->kdiv); in samsung_pll46xx_mpk_change()
607 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll46xx_set_rate() argument
610 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate()
618 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
619 return -EINVAL; in samsung_pll46xx_set_rate()
622 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
623 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
628 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; in samsung_pll46xx_set_rate()
629 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
634 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
635 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; in samsung_pll46xx_set_rate()
637 /* Maximum lock time bitfield is 16-bit. */ in samsung_pll46xx_set_rate()
641 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
650 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; in samsung_pll46xx_set_rate()
653 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | in samsung_pll46xx_set_rate()
654 (rate->pdiv << PLL46XX_PDIV_SHIFT) | in samsung_pll46xx_set_rate()
655 (rate->sdiv << PLL46XX_SDIV_SHIFT); in samsung_pll46xx_set_rate()
658 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
662 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | in samsung_pll46xx_set_rate()
663 (rate->mfr << PLL46XX_MFR_SHIFT) | in samsung_pll46xx_set_rate()
664 (rate->mrr << PLL46XX_MRR_SHIFT); in samsung_pll46xx_set_rate()
667 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
668 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
669 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
698 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, in samsung_pll6552_recalc_rate() argument
701 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate()
705 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
706 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
738 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, in samsung_pll6553_recalc_rate() argument
741 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate()
745 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
746 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
776 static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw, in samsung_s3c2410_pll_recalc_rate() argument
779 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_recalc_rate()
783 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_recalc_rate()
794 static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw, in samsung_s3c2440_mpll_recalc_rate() argument
797 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2440_mpll_recalc_rate()
801 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2440_mpll_recalc_rate()
812 static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_s3c2410_pll_set_rate() argument
815 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_set_rate()
823 drate, clk_hw_get_name(hw)); in samsung_s3c2410_pll_set_rate()
824 return -EINVAL; in samsung_s3c2410_pll_set_rate()
827 tmp = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_set_rate()
833 tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) | in samsung_s3c2410_pll_set_rate()
834 (rate->pdiv << PLLS3C2410_PDIV_SHIFT) | in samsung_s3c2410_pll_set_rate()
835 (rate->sdiv << PLLS3C2410_SDIV_SHIFT); in samsung_s3c2410_pll_set_rate()
836 writel_relaxed(tmp, pll->con_reg); in samsung_s3c2410_pll_set_rate()
838 /* Time to settle according to the manual */ in samsung_s3c2410_pll_set_rate()
844 static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable) in samsung_s3c2410_pll_enable() argument
846 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_enable()
847 u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
855 writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
857 /* if we started the UPLL, then allow to settle */ in samsung_s3c2410_pll_enable()
864 static int samsung_s3c2410_mpll_enable(struct clk_hw *hw) in samsung_s3c2410_mpll_enable() argument
866 return samsung_s3c2410_pll_enable(hw, 5, true); in samsung_s3c2410_mpll_enable()
869 static void samsung_s3c2410_mpll_disable(struct clk_hw *hw) in samsung_s3c2410_mpll_disable() argument
871 samsung_s3c2410_pll_enable(hw, 5, false); in samsung_s3c2410_mpll_disable()
874 static int samsung_s3c2410_upll_enable(struct clk_hw *hw) in samsung_s3c2410_upll_enable() argument
876 return samsung_s3c2410_pll_enable(hw, 7, true); in samsung_s3c2410_upll_enable()
879 static void samsung_s3c2410_upll_disable(struct clk_hw *hw) in samsung_s3c2410_upll_disable() argument
881 samsung_s3c2410_pll_enable(hw, 7, false); in samsung_s3c2410_upll_disable()
939 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, in samsung_pll2550x_recalc_rate() argument
942 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate()
946 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
968 /* Maximum lock time can be 270 * PDIV cycles */
980 static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, in samsung_pll2550xx_recalc_rate() argument
983 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate()
987 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1008 static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll2550xx_set_rate() argument
1011 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate()
1019 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate()
1020 return -EINVAL; in samsung_pll2550xx_set_rate()
1023 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1025 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { in samsung_pll2550xx_set_rate()
1028 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; in samsung_pll2550xx_set_rate()
1029 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1034 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1035 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1041 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | in samsung_pll2550xx_set_rate()
1042 (rate->pdiv << PLL2550XX_P_SHIFT) | in samsung_pll2550xx_set_rate()
1043 (rate->sdiv << PLL2550XX_S_SHIFT); in samsung_pll2550xx_set_rate()
1044 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1065 /* Maximum lock time can be 3000 * PDIV cycles */
1080 static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw, in samsung_pll2650x_recalc_rate() argument
1083 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate()
1088 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1093 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1103 static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll2650x_set_rate() argument
1106 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate()
1114 drate, clk_hw_get_name(hw)); in samsung_pll2650x_set_rate()
1115 return -EINVAL; in samsung_pll2650x_set_rate()
1118 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1119 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1121 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1122 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1128 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | in samsung_pll2650x_set_rate()
1129 (rate->pdiv << PLL2650X_P_SHIFT) | in samsung_pll2650x_set_rate()
1130 (rate->sdiv << PLL2650X_S_SHIFT); in samsung_pll2650x_set_rate()
1132 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1135 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); in samsung_pll2650x_set_rate()
1136 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1157 /* Maximum lock time can be 3000 * PDIV cycles */
1172 static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, in samsung_pll2650xx_recalc_rate() argument
1175 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate()
1180 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1181 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1194 static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, in samsung_pll2650xx_set_rate() argument
1197 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate()
1204 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
1205 return -EINVAL; in samsung_pll2650xx_set_rate()
1208 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1209 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1215 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; in samsung_pll2650xx_set_rate()
1216 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; in samsung_pll2650xx_set_rate()
1217 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; in samsung_pll2650xx_set_rate()
1222 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) in samsung_pll2650xx_set_rate()
1225 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1226 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1228 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1229 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1255 __func__, pll_clk->name); in _samsung_clk_register_pll()
1259 init.name = pll_clk->name; in _samsung_clk_register_pll()
1260 init.flags = pll_clk->flags; in _samsung_clk_register_pll()
1261 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll()
1264 if (pll_clk->rate_table) { in _samsung_clk_register_pll()
1266 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll()
1269 pll->rate_count = len; in _samsung_clk_register_pll()
1270 pll->rate_table = kmemdup(pll_clk->rate_table, in _samsung_clk_register_pll()
1271 pll->rate_count * in _samsung_clk_register_pll()
1274 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1276 __func__, pll_clk->name); in _samsung_clk_register_pll()
1279 switch (pll_clk->type) { in _samsung_clk_register_pll()
1292 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1293 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1294 if (!pll->rate_table) in _samsung_clk_register_pll()
1304 if (!pll->rate_table) in _samsung_clk_register_pll()
1312 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1313 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1314 if (!pll->rate_table) in _samsung_clk_register_pll()
1330 if (!pll->rate_table) in _samsung_clk_register_pll()
1336 if (!pll->rate_table) in _samsung_clk_register_pll()
1342 if (!pll->rate_table) in _samsung_clk_register_pll()
1348 if (!pll->rate_table) in _samsung_clk_register_pll()
1357 if (!pll->rate_table) in _samsung_clk_register_pll()
1363 if (!pll->rate_table) in _samsung_clk_register_pll()
1369 if (!pll->rate_table) in _samsung_clk_register_pll()
1376 __func__, pll_clk->name); in _samsung_clk_register_pll()
1379 pll->hw.init = &init; in _samsung_clk_register_pll()
1380 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1381 pll->lock_reg = base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1382 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
1384 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1387 __func__, pll_clk->name, ret); in _samsung_clk_register_pll()
1392 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()