Lines Matching full:pll
6 * This file contains the utility functions to register the pll clocks.
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
60 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
78 /* Wait until the PLL is locked */
79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, in samsung_pll_lock_wait() argument
99 if (readl_relaxed(pll->con_reg) & reg_mask) in samsung_pll_lock_wait()
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, in samsung_pll_lock_wait()
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
118 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
121 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
122 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
123 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll3xxx_enable()
130 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable() local
133 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
134 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
135 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
152 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
156 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
185 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
189 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
222 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate() local
226 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
251 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate() local
256 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
258 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll35xx_set_rate()
263 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
269 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
274 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
276 pll->lock_reg); in samsung_pll35xx_set_rate()
278 /* Change PLL PMS values */ in samsung_pll35xx_set_rate()
285 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
287 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll35xx_set_rate()
288 if (tmp & BIT(pll->enable_offs)) in samsung_pll35xx_set_rate()
289 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll35xx_set_rate()
326 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate() local
331 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
332 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
361 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate() local
365 rate = samsung_get_pll_settings(pll, drate); in samsung_pll36xx_set_rate()
367 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll36xx_set_rate()
372 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
373 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
379 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
384 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
385 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
387 /* Change PLL PMS values */ in samsung_pll36xx_set_rate()
394 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
398 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
400 if (pll_con0 & BIT(pll->enable_offs)) in samsung_pll36xx_set_rate()
401 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll36xx_set_rate()
439 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate() local
443 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
448 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
473 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate() local
478 rate = samsung_get_pll_settings(pll, drate); in samsung_pll45xx_set_rate()
480 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll45xx_set_rate()
485 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
486 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
492 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
497 /* Set PLL PMS values. */ in samsung_pll45xx_set_rate()
505 /* Set PLL AFC value. */ in samsung_pll45xx_set_rate()
506 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
510 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
511 switch (pll->type) { in samsung_pll45xx_set_rate()
513 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
516 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
523 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
524 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
526 /* Wait for PLL lock */ in samsung_pll45xx_set_rate()
527 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); in samsung_pll45xx_set_rate()
572 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate() local
576 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
577 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
578 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
582 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
585 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
610 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate() local
615 rate = samsung_get_pll_settings(pll, drate); in samsung_pll46xx_set_rate()
617 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll46xx_set_rate()
622 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
623 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
629 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
634 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
640 /* Set PLL PMS and VSEL values. */ in samsung_pll46xx_set_rate()
641 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
657 /* Set PLL K, MFR and MRR values. */ in samsung_pll46xx_set_rate()
658 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
666 /* Write configuration to PLL */ in samsung_pll46xx_set_rate()
667 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
668 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
669 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
671 /* Wait for PLL lock */ in samsung_pll46xx_set_rate()
672 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); in samsung_pll46xx_set_rate()
701 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate() local
705 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
706 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
741 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate() local
745 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
746 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
764 * PLL Clock Type of S3C24XX before S3C2443
779 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_recalc_rate() local
783 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_recalc_rate()
797 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2440_mpll_recalc_rate() local
801 pll_con = readl_relaxed(pll->con_reg); in samsung_s3c2440_mpll_recalc_rate()
815 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_set_rate() local
820 rate = samsung_get_pll_settings(pll, drate); in samsung_s3c2410_pll_set_rate()
822 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_s3c2410_pll_set_rate()
827 tmp = readl_relaxed(pll->con_reg); in samsung_s3c2410_pll_set_rate()
829 /* Change PLL PMS values */ in samsung_s3c2410_pll_set_rate()
836 writel_relaxed(tmp, pll->con_reg); in samsung_s3c2410_pll_set_rate()
846 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_s3c2410_pll_enable() local
847 u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
855 writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); in samsung_s3c2410_pll_enable()
942 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate() local
946 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
983 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate() local
987 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1011 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate() local
1016 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2550xx_set_rate()
1018 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2550xx_set_rate()
1023 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1029 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1034 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1035 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1037 /* Change PLL PMS values */ in samsung_pll2550xx_set_rate()
1044 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1046 /* Wait for PLL lock */ in samsung_pll2550xx_set_rate()
1047 return samsung_pll_lock_wait(pll, in samsung_pll2550xx_set_rate()
1083 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate() local
1088 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1093 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1106 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate() local
1111 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650x_set_rate()
1113 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650x_set_rate()
1118 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1119 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1121 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1122 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1124 /* Change PLL PMS values */ in samsung_pll2650x_set_rate()
1132 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1136 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1138 /* Wait for PLL lock */ in samsung_pll2650x_set_rate()
1139 return samsung_pll_lock_wait(pll, in samsung_pll2650x_set_rate()
1175 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate() local
1180 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1181 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1197 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate() local
1201 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650xx_set_rate()
1203 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650xx_set_rate()
1208 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1209 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1211 /* Change PLL PMS values */ in samsung_pll2650xx_set_rate()
1225 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1226 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1228 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1229 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1231 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); in samsung_pll2650xx_set_rate()
1248 struct samsung_clk_pll *pll; in _samsung_clk_register_pll() local
1252 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _samsung_clk_register_pll()
1253 if (!pll) { in _samsung_clk_register_pll()
1254 pr_err("%s: could not allocate pll clk %s\n", in _samsung_clk_register_pll()
1269 pll->rate_count = len; in _samsung_clk_register_pll()
1270 pll->rate_table = kmemdup(pll_clk->rate_table, in _samsung_clk_register_pll()
1271 pll->rate_count * in _samsung_clk_register_pll()
1274 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1292 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1293 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1294 if (!pll->rate_table) in _samsung_clk_register_pll()
1304 if (!pll->rate_table) in _samsung_clk_register_pll()
1312 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1313 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1314 if (!pll->rate_table) in _samsung_clk_register_pll()
1330 if (!pll->rate_table) in _samsung_clk_register_pll()
1336 if (!pll->rate_table) in _samsung_clk_register_pll()
1342 if (!pll->rate_table) in _samsung_clk_register_pll()
1348 if (!pll->rate_table) in _samsung_clk_register_pll()
1357 if (!pll->rate_table) in _samsung_clk_register_pll()
1363 if (!pll->rate_table) in _samsung_clk_register_pll()
1369 if (!pll->rate_table) in _samsung_clk_register_pll()
1375 pr_warn("%s: Unknown pll type for pll clk %s\n", in _samsung_clk_register_pll()
1379 pll->hw.init = &init; in _samsung_clk_register_pll()
1380 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1381 pll->lock_reg = base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1382 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
1384 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1386 pr_err("%s: failed to register pll clock %s : %d\n", in _samsung_clk_register_pll()
1388 kfree(pll); in _samsung_clk_register_pll()
1392 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()