1 // SPDX-License-Identifier: GPL-2.0
7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47  * R-Car Gen2, R-Car Gen3, and RZ/G1.
48  * These are NOT valid for R-Car Gen1 and RZ/A1!
118  * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
122  * @dev: CPG/MSSR device
123  * @base: CPG/MSSR register block base address
124  * @reg_layout: CPG/MSSR register layout
126  * @np: Device node in DT for this CPG/MSSR module
127  * @num_core_clks: Number of Core Clocks in clks[]
128  * @num_mod_clks: Number of Module Clocks in clks[]
137  * @clks: Array containing all Core and Module Clocks
169  * struct mstp_clock - MSTP gating clock
170  * @hw: handle between common and hardware-specific interfaces
171  * @index: MSTP clock number
172  * @priv: CPG/MSSR private data
185 	struct cpg_mssr_priv *priv = clock->priv;  in cpg_mstp_clock_endisable()
186 	unsigned int reg = clock->index / 32;  in cpg_mstp_clock_endisable()
187 	unsigned int bit = clock->index % 32;  in cpg_mstp_clock_endisable()
188 	struct device *dev = priv->dev;  in cpg_mstp_clock_endisable()
194 	dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,  in cpg_mstp_clock_endisable()
196 	spin_lock_irqsave(&priv->rmw_lock, flags);  in cpg_mstp_clock_endisable()
198 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mstp_clock_endisable()
199 		value = readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
204 		writeb(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
207 		readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
208 		barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
210 		value = readl(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
215 		writel(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
218 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in cpg_mstp_clock_endisable()
220 	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mstp_clock_endisable()
223 	for (i = 1000; i > 0; --i) {  in cpg_mstp_clock_endisable()
224 		if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))  in cpg_mstp_clock_endisable()
231 			priv->base + priv->control_regs[reg], bit);  in cpg_mstp_clock_endisable()
232 		return -ETIMEDOUT;  in cpg_mstp_clock_endisable()
251 	struct cpg_mssr_priv *priv = clock->priv;  in cpg_mstp_clock_is_enabled()
254 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mstp_clock_is_enabled()
255 		value = readb(priv->base + priv->control_regs[clock->index / 32]);  in cpg_mstp_clock_is_enabled()
257 		value = readl(priv->base + priv->status_regs[clock->index / 32]);  in cpg_mstp_clock_is_enabled()
259 	return !(value & BIT(clock->index % 32));  in cpg_mstp_clock_is_enabled()
272 	unsigned int clkidx = clkspec->args[1];  in cpg_mssr_clk_src_twocell_get()
274 	struct device *dev = priv->dev;  in cpg_mssr_clk_src_twocell_get()
280 	switch (clkspec->args[0]) {  in cpg_mssr_clk_src_twocell_get()
283 		if (clkidx > priv->last_dt_core_clk) {  in cpg_mssr_clk_src_twocell_get()
286 			return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
288 		clk = priv->clks[clkidx];  in cpg_mssr_clk_src_twocell_get()
293 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_clk_src_twocell_get()
295 			range_check = 7 - (clkidx % 10);  in cpg_mssr_clk_src_twocell_get()
298 			range_check = 31 - (clkidx % 100);  in cpg_mssr_clk_src_twocell_get()
300 		if (range_check < 0 || idx >= priv->num_mod_clks) {  in cpg_mssr_clk_src_twocell_get()
303 			return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
305 		clk = priv->clks[priv->num_core_clks + idx];  in cpg_mssr_clk_src_twocell_get()
309 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);  in cpg_mssr_clk_src_twocell_get()
310 		return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
318 			clkspec->args[0], clkspec->args[1], clk,  in cpg_mssr_clk_src_twocell_get()
327 	struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;  in cpg_mssr_register_core_clk()
328 	struct device *dev = priv->dev;  in cpg_mssr_register_core_clk()
329 	unsigned int id = core->id, div = core->div;  in cpg_mssr_register_core_clk()
332 	WARN_DEBUG(id >= priv->num_core_clks);  in cpg_mssr_register_core_clk()
333 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in cpg_mssr_register_core_clk()
335 	if (!core->name) {  in cpg_mssr_register_core_clk()
340 	switch (core->type) {  in cpg_mssr_register_core_clk()
342 		clk = of_clk_get_by_name(priv->np, core->name);  in cpg_mssr_register_core_clk()
348 		WARN_DEBUG(core->parent >= priv->num_core_clks);  in cpg_mssr_register_core_clk()
349 		parent = priv->clks[core->parent];  in cpg_mssr_register_core_clk()
357 		if (core->type == CLK_TYPE_DIV6_RO)  in cpg_mssr_register_core_clk()
359 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;  in cpg_mssr_register_core_clk()
361 		if (core->type == CLK_TYPE_DIV6P1) {  in cpg_mssr_register_core_clk()
362 			clk = cpg_div6_register(core->name, 1, &parent_name,  in cpg_mssr_register_core_clk()
363 						priv->base + core->offset,  in cpg_mssr_register_core_clk()
364 						&priv->notifiers);  in cpg_mssr_register_core_clk()
366 			clk = clk_register_fixed_factor(NULL, core->name,  in cpg_mssr_register_core_clk()
368 							core->mult, div);  in cpg_mssr_register_core_clk()
373 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,  in cpg_mssr_register_core_clk()
374 					      core->mult);  in cpg_mssr_register_core_clk()
378 		if (info->cpg_clk_register)  in cpg_mssr_register_core_clk()
379 			clk = info->cpg_clk_register(dev, core, info,  in cpg_mssr_register_core_clk()
380 						     priv->clks, priv->base,  in cpg_mssr_register_core_clk()
381 						     &priv->notifiers);  in cpg_mssr_register_core_clk()
384 				core->name, core->type);  in cpg_mssr_register_core_clk()
392 	priv->clks[id] = clk;  in cpg_mssr_register_core_clk()
397 		core->name, PTR_ERR(clk));  in cpg_mssr_register_core_clk()
405 	struct device *dev = priv->dev;  in cpg_mssr_register_mod_clk()
406 	unsigned int id = mod->id;  in cpg_mssr_register_mod_clk()
412 	WARN_DEBUG(id < priv->num_core_clks);  in cpg_mssr_register_mod_clk()
413 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);  in cpg_mssr_register_mod_clk()
414 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);  in cpg_mssr_register_mod_clk()
415 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in cpg_mssr_register_mod_clk()
417 	if (!mod->name) {  in cpg_mssr_register_mod_clk()
422 	parent = priv->clks[mod->parent];  in cpg_mssr_register_mod_clk()
430 		clk = ERR_PTR(-ENOMEM);  in cpg_mssr_register_mod_clk()
434 	init.name = mod->name;  in cpg_mssr_register_mod_clk()
441 	clock->index = id - priv->num_core_clks;  in cpg_mssr_register_mod_clk()
442 	clock->priv = priv;  in cpg_mssr_register_mod_clk()
443 	clock->hw.init = &init;  in cpg_mssr_register_mod_clk()
445 	for (i = 0; i < info->num_crit_mod_clks; i++)  in cpg_mssr_register_mod_clk()
446 		if (id == info->crit_mod_clks[i] &&  in cpg_mssr_register_mod_clk()
447 		    cpg_mstp_clock_is_enabled(&clock->hw)) {  in cpg_mssr_register_mod_clk()
448 			dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",  in cpg_mssr_register_mod_clk()
449 				mod->name);  in cpg_mssr_register_mod_clk()
454 	clk = clk_register(NULL, &clock->hw);  in cpg_mssr_register_mod_clk()
459 	priv->clks[id] = clk;  in cpg_mssr_register_mod_clk()
460 	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);  in cpg_mssr_register_mod_clk()
465 		mod->name, PTR_ERR(clk));  in cpg_mssr_register_mod_clk()
482 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)  in cpg_mssr_is_pm_clk()
485 	switch (clkspec->args[0]) {  in cpg_mssr_is_pm_clk()
487 		for (i = 0; i < pd->num_core_pm_clks; i++)  in cpg_mssr_is_pm_clk()
488 			if (clkspec->args[1] == pd->core_pm_clks[i])  in cpg_mssr_is_pm_clk()
503 	struct device_node *np = dev->of_node;  in cpg_mssr_attach_dev()
510 		dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");  in cpg_mssr_attach_dev()
511 		return -EPROBE_DEFER;  in cpg_mssr_attach_dev()
514 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,  in cpg_mssr_attach_dev()
559 	struct device_node *np = dev->of_node;  in cpg_mssr_add_clk_domain()
566 		return -ENOMEM;  in cpg_mssr_add_clk_domain()
568 	pd->num_core_pm_clks = num_core_pm_clks;  in cpg_mssr_add_clk_domain()
569 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);  in cpg_mssr_add_clk_domain()
571 	genpd = &pd->genpd;  in cpg_mssr_add_clk_domain()
572 	genpd->name = np->name;  in cpg_mssr_add_clk_domain()
573 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |  in cpg_mssr_add_clk_domain()
575 	genpd->attach_dev = cpg_mssr_attach_dev;  in cpg_mssr_add_clk_domain()
576 	genpd->detach_dev = cpg_mssr_detach_dev;  in cpg_mssr_add_clk_domain()
596 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);  in cpg_mssr_reset()
599 	writel(bitmask, priv->base + priv->reset_regs[reg]);  in cpg_mssr_reset()
605 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);  in cpg_mssr_reset()
617 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);  in cpg_mssr_assert()
619 	writel(bitmask, priv->base + priv->reset_regs[reg]);  in cpg_mssr_assert()
631 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);  in cpg_mssr_deassert()
633 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);  in cpg_mssr_deassert()
645 	return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);  in cpg_mssr_status()
659 	unsigned int unpacked = reset_spec->args[0];  in cpg_mssr_reset_xlate()
662 	if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {  in cpg_mssr_reset_xlate()
663 		dev_err(priv->dev, "Invalid reset index %u\n", unpacked);  in cpg_mssr_reset_xlate()
664 		return -EINVAL;  in cpg_mssr_reset_xlate()
672 	priv->rcdev.ops = &cpg_mssr_reset_ops;  in cpg_mssr_reset_controller_register()
673 	priv->rcdev.of_node = priv->dev->of_node;  in cpg_mssr_reset_controller_register()
674 	priv->rcdev.of_reset_n_cells = 1;  in cpg_mssr_reset_controller_register()
675 	priv->rcdev.of_xlate = cpg_mssr_reset_xlate;  in cpg_mssr_reset_controller_register()
676 	priv->rcdev.nr_resets = priv->num_mod_clks;  in cpg_mssr_reset_controller_register()
677 	return devm_reset_controller_register(priv->dev, &priv->rcdev);  in cpg_mssr_reset_controller_register()
691 		.compatible = "renesas,r7s9210-cpg-mssr",
697 		.compatible = "renesas,r8a7742-cpg-mssr",
703 		.compatible = "renesas,r8a7743-cpg-mssr",
706 	/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
708 		.compatible = "renesas,r8a7744-cpg-mssr",
714 		.compatible = "renesas,r8a7745-cpg-mssr",
720 		.compatible = "renesas,r8a77470-cpg-mssr",
726 		.compatible = "renesas,r8a774a1-cpg-mssr",
732 		.compatible = "renesas,r8a774b1-cpg-mssr",
738 		.compatible = "renesas,r8a774c0-cpg-mssr",
744 		.compatible = "renesas,r8a774e1-cpg-mssr",
750 		.compatible = "renesas,r8a7790-cpg-mssr",
756 		.compatible = "renesas,r8a7791-cpg-mssr",
759 	/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
761 		.compatible = "renesas,r8a7793-cpg-mssr",
767 		.compatible = "renesas,r8a7792-cpg-mssr",
773 		.compatible = "renesas,r8a7794-cpg-mssr",
779 		.compatible = "renesas,r8a7795-cpg-mssr",
785 		.compatible = "renesas,r8a7796-cpg-mssr",
791 		.compatible = "renesas,r8a77961-cpg-mssr",
797 		.compatible = "renesas,r8a77965-cpg-mssr",
803 		.compatible = "renesas,r8a77970-cpg-mssr",
809 		.compatible = "renesas,r8a77980-cpg-mssr",
815 		.compatible = "renesas,r8a77990-cpg-mssr",
821 		.compatible = "renesas,r8a77995-cpg-mssr",
827 		.compatible = "renesas,r8a779a0-cpg-mssr",
850 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_suspend_noirq()
851 		if (priv->smstpcr_saved[reg].mask)  in cpg_mssr_suspend_noirq()
852 			priv->smstpcr_saved[reg].val =  in cpg_mssr_suspend_noirq()
853 				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?  in cpg_mssr_suspend_noirq()
854 				readb(priv->base + priv->control_regs[reg]) :  in cpg_mssr_suspend_noirq()
855 				readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_suspend_noirq()
858 	/* Save core clocks */  in cpg_mssr_suspend_noirq()
859 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);  in cpg_mssr_suspend_noirq()
874 	/* Restore core clocks */  in cpg_mssr_resume_noirq()
875 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);  in cpg_mssr_resume_noirq()
877 	/* Restore module clocks */  in cpg_mssr_resume_noirq()
878 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_resume_noirq()
879 		mask = priv->smstpcr_saved[reg].mask;  in cpg_mssr_resume_noirq()
883 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mssr_resume_noirq()
884 			oldval = readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
886 			oldval = readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
888 		newval |= priv->smstpcr_saved[reg].val & mask;  in cpg_mssr_resume_noirq()
892 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_resume_noirq()
893 			writeb(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
895 			readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
896 			barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
899 			writel(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
901 		/* Wait until enabled clocks are really enabled */  in cpg_mssr_resume_noirq()
902 		mask &= ~priv->smstpcr_saved[reg].val;  in cpg_mssr_resume_noirq()
906 		for (i = 1000; i > 0; --i) {  in cpg_mssr_resume_noirq()
907 			oldval = readl(priv->base + priv->status_regs[reg]);  in cpg_mssr_resume_noirq()
915 				 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?  in cpg_mssr_resume_noirq()
939 	if (info->init) {  in cpg_mssr_common_init()
940 		error = info->init(dev);  in cpg_mssr_common_init()
945 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;  in cpg_mssr_common_init()
948 		return -ENOMEM;  in cpg_mssr_common_init()
950 	priv->np = np;  in cpg_mssr_common_init()
951 	priv->dev = dev;  in cpg_mssr_common_init()
952 	spin_lock_init(&priv->rmw_lock);  in cpg_mssr_common_init()
954 	priv->base = of_iomap(np, 0);  in cpg_mssr_common_init()
955 	if (!priv->base) {  in cpg_mssr_common_init()
956 		error = -ENOMEM;  in cpg_mssr_common_init()
961 	priv->num_core_clks = info->num_total_core_clks;  in cpg_mssr_common_init()
962 	priv->num_mod_clks = info->num_hw_mod_clks;  in cpg_mssr_common_init()
963 	priv->last_dt_core_clk = info->last_dt_core_clk;  in cpg_mssr_common_init()
964 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);  in cpg_mssr_common_init()
965 	priv->reg_layout = info->reg_layout;  in cpg_mssr_common_init()
966 	if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {  in cpg_mssr_common_init()
967 		priv->status_regs = mstpsr;  in cpg_mssr_common_init()
968 		priv->control_regs = smstpcr;  in cpg_mssr_common_init()
969 		priv->reset_regs = srcr;  in cpg_mssr_common_init()
970 		priv->reset_clear_regs = srstclr;  in cpg_mssr_common_init()
971 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_common_init()
972 		priv->control_regs = stbcr;  in cpg_mssr_common_init()
973 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {  in cpg_mssr_common_init()
974 		priv->status_regs = mstpsr_for_v3u;  in cpg_mssr_common_init()
975 		priv->control_regs = mstpcr_for_v3u;  in cpg_mssr_common_init()
976 		priv->reset_regs = srcr_for_v3u;  in cpg_mssr_common_init()
977 		priv->reset_clear_regs = srstclr_for_v3u;  in cpg_mssr_common_init()
979 		error = -EINVAL;  in cpg_mssr_common_init()
984 		priv->clks[i] = ERR_PTR(-ENOENT);  in cpg_mssr_common_init()
993 	if (priv->base)  in cpg_mssr_common_init()
994 		iounmap(priv->base);  in cpg_mssr_common_init()
1010 	for (i = 0; i < info->num_early_core_clks; i++)  in cpg_mssr_early_init()
1011 		cpg_mssr_register_core_clk(&info->early_core_clks[i], info,  in cpg_mssr_early_init()
1014 	for (i = 0; i < info->num_early_mod_clks; i++)  in cpg_mssr_early_init()
1015 		cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,  in cpg_mssr_early_init()
1022 	struct device *dev = &pdev->dev;  in cpg_mssr_probe()
1023 	struct device_node *np = dev->of_node;  in cpg_mssr_probe()
1032 		error = cpg_mssr_common_init(dev, dev->of_node, info);  in cpg_mssr_probe()
1038 	priv->dev = dev;  in cpg_mssr_probe()
1041 	for (i = 0; i < info->num_core_clks; i++)  in cpg_mssr_probe()
1042 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);  in cpg_mssr_probe()
1044 	for (i = 0; i < info->num_mod_clks; i++)  in cpg_mssr_probe()
1045 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);  in cpg_mssr_probe()
1053 	error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,  in cpg_mssr_probe()
1054 					info->num_core_pm_clks);  in cpg_mssr_probe()
1059 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mssr_probe()
1071 		.name	= "renesas-cpg-mssr",
1124 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");