Lines Matching +full:0 +full:x3b00
65 { 0x0, 1 },
66 { 0x1, 2 },
67 { 0x3, 4 },
68 { 0x7, 8 },
73 .offset = 0xc000,
76 .enable_reg = 0x1e0,
77 .enable_mask = BIT(0),
91 .offset = 0xc000,
106 .offset = 0xc050,
109 .enable_reg = 0x1e0,
124 .offset = 0xc050,
139 .offset = 0x0,
153 .offset = 0x0,
168 .offset = 0x50,
182 .offset = 0x50,
197 .offset = 0xa0,
211 .offset = 0xa0,
226 .offset = 0xf0,
240 .offset = 0xf0,
255 .offset = 0x140,
269 .offset = 0x140,
284 .offset = 0x190,
298 .offset = 0x190,
313 { P_XO, 0 },
325 { P_XO, 0 },
339 { P_XO, 0 },
353 { P_XO, 0 },
367 { P_XO, 0 },
381 { P_XO, 0 },
397 { P_XO, 0 },
415 { P_XO, 0 },
433 { P_XO, 0 },
453 { P_XO, 0 },
473 { P_XO, 0 },
493 { P_XO, 0 },
515 .cmd_rcgr = 0x2120,
528 .cmd_rcgr = 0x2140,
541 F(37500000, P_GPLL0, 16, 0, 0),
542 F(50000000, P_GPLL0, 12, 0, 0),
543 F(100000000, P_GPLL0, 6, 0, 0),
548 .cmd_rcgr = 0x3300,
561 F(100000000, P_GPLL0, 6, 0, 0),
562 F(200000000, P_GPLL0, 3, 0, 0),
563 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
564 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
565 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
566 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
567 F(600000000, P_GPLL0, 1, 0, 0),
572 .cmd_rcgr = 0x3640,
585 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
586 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
587 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
588 F(300000000, P_GPLL0, 2, 0, 0),
589 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
590 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
595 .cmd_rcgr = 0x3090,
608 .cmd_rcgr = 0x3100,
621 .cmd_rcgr = 0x3160,
634 .cmd_rcgr = 0x31c0,
647 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
648 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
649 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
650 F(300000000, P_GPLL0, 2, 0, 0),
651 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
656 .cmd_rcgr = 0x3800,
669 F(200000000, P_GPLL0, 3, 0, 0),
670 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
675 .cmd_rcgr = 0x3000,
688 .cmd_rcgr = 0x3030,
701 .cmd_rcgr = 0x3060,
714 F(19200000, P_XO, 1, 0, 0),
719 .cmd_rcgr = 0x2260,
739 .cmd_rcgr = 0x2220,
752 F(162000, P_DPLINK, 2, 0, 0),
753 F(270000, P_DPLINK, 2, 0, 0),
754 F(540000, P_DPLINK, 2, 0, 0),
759 .cmd_rcgr = 0x2200,
772 F(154000000, P_DPVCO, 1, 0, 0),
773 F(337500000, P_DPVCO, 2, 0, 0),
774 F(675000000, P_DPVCO, 2, 0, 0),
779 .cmd_rcgr = 0x2240,
792 F(19200000, P_XO, 1, 0, 0),
797 .cmd_rcgr = 0x2160,
810 .cmd_rcgr = 0x2180,
828 .cmd_rcgr = 0x2060,
842 F(100000000, P_GPLL0, 6, 0, 0),
843 F(200000000, P_GPLL0, 3, 0, 0),
844 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
845 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
846 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
851 .cmd_rcgr = 0x3b00,
864 F(19200000, P_XO, 1, 0, 0),
869 .cmd_rcgr = 0x2100,
882 F(75000000, P_GPLL0, 8, 0, 0),
883 F(150000000, P_GPLL0, 4, 0, 0),
884 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
885 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
890 .cmd_rcgr = 0x3500,
903 F(19200000, P_XO, 1, 0, 0),
904 F(75000000, P_GPLL0_DIV, 4, 0, 0),
905 F(171428571, P_GPLL0, 3.5, 0, 0),
906 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
907 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
912 .cmd_rcgr = 0xf020,
925 F(4800000, P_XO, 4, 0, 0),
928 F(9600000, P_XO, 2, 0, 0),
930 F(19200000, P_XO, 1, 0, 0),
939 .cmd_rcgr = 0x3360,
952 .cmd_rcgr = 0x3390,
965 .cmd_rcgr = 0x33c0,
978 .cmd_rcgr = 0x33f0,
991 F(85714286, P_GPLL0, 7, 0, 0),
992 F(100000000, P_GPLL0, 6, 0, 0),
993 F(150000000, P_GPLL0, 4, 0, 0),
994 F(171428571, P_GPLL0, 3.5, 0, 0),
995 F(200000000, P_GPLL0, 3, 0, 0),
996 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
997 F(300000000, P_GPLL0, 2, 0, 0),
998 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
999 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1004 .cmd_rcgr = 0x2040,
1017 F(19200000, P_XO, 1, 0, 0),
1022 .cmd_rcgr = 0x2080,
1035 F(19200000, P_XO, 1, 0, 0),
1036 F(40000000, P_GPLL0, 15, 0, 0),
1037 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1042 .cmd_rcgr = 0x5000,
1055 F(75000000, P_GPLL0, 8, 0, 0),
1056 F(171428571, P_GPLL0, 3.5, 0, 0),
1057 F(240000000, P_GPLL0, 2.5, 0, 0),
1058 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1059 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1065 .cmd_rcgr = 0xd000,
1078 .cmd_rcgr = 0x2000,
1092 .cmd_rcgr = 0x2020,
1106 F(171428571, P_GPLL0, 3.5, 0, 0),
1107 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1108 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1109 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1114 .cmd_rcgr = 0x21a0,
1127 F(200000000, P_GPLL0, 3, 0, 0),
1128 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1129 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1130 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1131 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1136 .cmd_rcgr = 0x1000,
1149 .cmd_rcgr = 0x1060,
1162 .cmd_rcgr = 0x1080,
1175 F(200000000, P_GPLL0, 3, 0, 0),
1176 F(300000000, P_GPLL0, 2, 0, 0),
1177 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1178 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1179 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1180 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1181 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1182 F(600000000, P_GPLL0, 1, 0, 0),
1187 .cmd_rcgr = 0x3600,
1200 .cmd_rcgr = 0x3620,
1213 .halt_reg = 0x328,
1214 .hwcg_reg = 0x328,
1217 .enable_reg = 0x328,
1218 .enable_mask = BIT(0),
1230 .halt_reg = 0x1028,
1232 .enable_reg = 0x1028,
1233 .enable_mask = BIT(0),
1245 .halt_reg = 0x1030,
1246 .hwcg_reg = 0x1030,
1249 .enable_reg = 0x1030,
1250 .enable_mask = BIT(0),
1262 .halt_reg = 0x1034,
1264 .enable_reg = 0x1034,
1265 .enable_mask = BIT(0),
1276 .halt_reg = 0x1038,
1278 .enable_reg = 0x1038,
1279 .enable_mask = BIT(0),
1291 .halt_reg = 0x1048,
1293 .enable_reg = 0x1048,
1294 .enable_mask = BIT(0),
1306 .halt_reg = 0x104c,
1308 .enable_reg = 0x104c,
1309 .enable_mask = BIT(0),
1321 .halt_reg = 0x2308,
1322 .hwcg_reg = 0x2308,
1325 .enable_reg = 0x2308,
1326 .enable_mask = BIT(0),
1338 .halt_reg = 0x230c,
1340 .enable_reg = 0x230c,
1341 .enable_mask = BIT(0),
1353 .halt_reg = 0x2310,
1355 .enable_reg = 0x2310,
1356 .enable_mask = BIT(0),
1367 .halt_reg = 0x2314,
1369 .enable_reg = 0x2314,
1370 .enable_mask = BIT(0),
1382 .halt_reg = 0x2318,
1384 .enable_reg = 0x2318,
1385 .enable_mask = BIT(0),
1397 .halt_reg = 0x231c,
1399 .enable_reg = 0x231c,
1400 .enable_mask = BIT(0),
1412 .halt_reg = 0x2320,
1414 .enable_reg = 0x2320,
1415 .enable_mask = BIT(0),
1427 .halt_reg = 0x2324,
1429 .enable_reg = 0x2324,
1430 .enable_mask = BIT(0),
1442 .halt_reg = 0x2328,
1444 .enable_reg = 0x2328,
1445 .enable_mask = BIT(0),
1457 .halt_reg = 0x2338,
1459 .enable_reg = 0x2338,
1460 .enable_mask = BIT(0),
1472 .halt_reg = 0x233c,
1474 .enable_reg = 0x233c,
1475 .enable_mask = BIT(0),
1487 .halt_reg = 0x2340,
1489 .enable_reg = 0x2340,
1490 .enable_mask = BIT(0),
1502 .halt_reg = 0x2344,
1504 .enable_reg = 0x2344,
1505 .enable_mask = BIT(0),
1517 .halt_reg = 0x2348,
1519 .enable_reg = 0x2348,
1520 .enable_mask = BIT(0),
1532 .halt_reg = 0x2350,
1534 .enable_reg = 0x2350,
1535 .enable_mask = BIT(0),
1547 .halt_reg = 0x2354,
1549 .enable_reg = 0x2354,
1550 .enable_mask = BIT(0),
1562 .halt_reg = 0x2358,
1564 .enable_reg = 0x2358,
1565 .enable_mask = BIT(0),
1577 .halt_reg = 0x235c,
1579 .enable_reg = 0x235c,
1580 .enable_mask = BIT(0),
1592 .halt_reg = 0x2360,
1594 .enable_reg = 0x2360,
1595 .enable_mask = BIT(0),
1607 .halt_reg = 0x2364,
1609 .enable_reg = 0x2364,
1610 .enable_mask = BIT(0),
1622 .halt_reg = 0x2374,
1624 .enable_reg = 0x2374,
1625 .enable_mask = BIT(0),
1637 .halt_reg = 0x2378,
1639 .enable_reg = 0x2378,
1640 .enable_mask = BIT(0),
1652 .halt_reg = 0x3024,
1654 .enable_reg = 0x3024,
1655 .enable_mask = BIT(0),
1667 .halt_reg = 0x3054,
1669 .enable_reg = 0x3054,
1670 .enable_mask = BIT(0),
1682 .halt_reg = 0x3084,
1684 .enable_reg = 0x3084,
1685 .enable_mask = BIT(0),
1697 .halt_reg = 0x30b4,
1699 .enable_reg = 0x30b4,
1700 .enable_mask = BIT(0),
1712 .halt_reg = 0x30bc,
1714 .enable_reg = 0x30bc,
1715 .enable_mask = BIT(0),
1727 .halt_reg = 0x30d4,
1729 .enable_reg = 0x30d4,
1730 .enable_mask = BIT(0),
1742 .halt_reg = 0x30e4,
1744 .enable_reg = 0x30e4,
1745 .enable_mask = BIT(0),
1757 .halt_reg = 0x3124,
1759 .enable_reg = 0x3124,
1760 .enable_mask = BIT(0),
1772 .halt_reg = 0x3128,
1774 .enable_reg = 0x3128,
1775 .enable_mask = BIT(0),
1787 .halt_reg = 0x3144,
1789 .enable_reg = 0x3144,
1790 .enable_mask = BIT(0),
1802 .halt_reg = 0x3154,
1804 .enable_reg = 0x3154,
1805 .enable_mask = BIT(0),
1817 .halt_reg = 0x3184,
1819 .enable_reg = 0x3184,
1820 .enable_mask = BIT(0),
1832 .halt_reg = 0x3188,
1834 .enable_reg = 0x3188,
1835 .enable_mask = BIT(0),
1847 .halt_reg = 0x31a4,
1849 .enable_reg = 0x31a4,
1850 .enable_mask = BIT(0),
1862 .halt_reg = 0x31b4,
1864 .enable_reg = 0x31b4,
1865 .enable_mask = BIT(0),
1877 .halt_reg = 0x31e4,
1879 .enable_reg = 0x31e4,
1880 .enable_mask = BIT(0),
1892 .halt_reg = 0x31e8,
1894 .enable_reg = 0x31e8,
1895 .enable_mask = BIT(0),
1907 .halt_reg = 0x3204,
1909 .enable_reg = 0x3204,
1910 .enable_mask = BIT(0),
1922 .halt_reg = 0x3214,
1924 .enable_reg = 0x3214,
1925 .enable_mask = BIT(0),
1937 .halt_reg = 0x3224,
1939 .enable_reg = 0x3224,
1940 .enable_mask = BIT(0),
1952 .halt_reg = 0x3344,
1954 .enable_reg = 0x3344,
1955 .enable_mask = BIT(0),
1967 .halt_reg = 0x3348,
1969 .enable_reg = 0x3348,
1970 .enable_mask = BIT(0),
1982 .halt_reg = 0x3384,
1984 .enable_reg = 0x3384,
1985 .enable_mask = BIT(0),
1997 .halt_reg = 0x33b4,
1999 .enable_reg = 0x33b4,
2000 .enable_mask = BIT(0),
2012 .halt_reg = 0x33e4,
2014 .enable_reg = 0x33e4,
2015 .enable_mask = BIT(0),
2027 .halt_reg = 0x3414,
2029 .enable_reg = 0x3414,
2030 .enable_mask = BIT(0),
2042 .halt_reg = 0x3484,
2044 .enable_reg = 0x3484,
2045 .enable_mask = BIT(0),
2057 .halt_reg = 0x348c,
2059 .enable_reg = 0x348c,
2060 .enable_mask = BIT(0),
2072 .halt_reg = 0x3494,
2074 .enable_reg = 0x3494,
2075 .enable_mask = BIT(0),
2087 .halt_reg = 0x35a8,
2089 .enable_reg = 0x35a8,
2090 .enable_mask = BIT(0),
2102 .halt_reg = 0x35b4,
2104 .enable_reg = 0x35b4,
2105 .enable_mask = BIT(0),
2117 .halt_reg = 0x35b8,
2119 .enable_reg = 0x35b8,
2120 .enable_mask = BIT(0),
2131 .halt_reg = 0x3668,
2133 .enable_reg = 0x3668,
2134 .enable_mask = BIT(0),
2146 .halt_reg = 0x3678,
2148 .enable_reg = 0x3678,
2149 .enable_mask = BIT(0),
2161 .halt_reg = 0x36a8,
2163 .enable_reg = 0x36a8,
2164 .enable_mask = BIT(0),
2176 .halt_reg = 0x36ac,
2178 .enable_reg = 0x36ac,
2179 .enable_mask = BIT(0),
2191 .halt_reg = 0x36b0,
2193 .enable_reg = 0x36b0,
2194 .enable_mask = BIT(0),
2206 .halt_reg = 0x36b4,
2208 .enable_reg = 0x36b4,
2209 .enable_mask = BIT(0),
2221 .halt_reg = 0x36b8,
2223 .enable_reg = 0x36b8,
2224 .enable_mask = BIT(0),
2236 .halt_reg = 0x36bc,
2238 .enable_reg = 0x36bc,
2239 .enable_mask = BIT(0),
2250 .halt_reg = 0x36c4,
2252 .enable_reg = 0x36c4,
2253 .enable_mask = BIT(0),
2264 .halt_reg = 0x36c8,
2266 .enable_reg = 0x36c8,
2267 .enable_mask = BIT(0),
2279 .halt_reg = 0x3704,
2281 .enable_reg = 0x3704,
2282 .enable_mask = BIT(0),
2294 .halt_reg = 0x3714,
2296 .enable_reg = 0x3714,
2297 .enable_mask = BIT(0),
2309 .halt_reg = 0x3720,
2311 .enable_reg = 0x3720,
2312 .enable_mask = BIT(0),
2324 .halt_reg = 0x3724,
2326 .enable_reg = 0x3724,
2327 .enable_mask = BIT(0),
2339 .halt_reg = 0x3730,
2341 .enable_reg = 0x3730,
2342 .enable_mask = BIT(0),
2354 .halt_reg = 0x3734,
2356 .enable_reg = 0x3734,
2357 .enable_mask = BIT(0),
2369 .halt_reg = 0x3738,
2371 .enable_reg = 0x3738,
2372 .enable_mask = BIT(0),
2384 .halt_reg = 0x373c,
2386 .enable_reg = 0x373c,
2387 .enable_mask = BIT(0),
2399 .halt_reg = 0x3740,
2401 .enable_reg = 0x3740,
2402 .enable_mask = BIT(0),
2414 .halt_reg = 0x3744,
2416 .enable_reg = 0x3744,
2417 .enable_mask = BIT(0),
2429 .halt_reg = 0x3748,
2431 .enable_reg = 0x3748,
2432 .enable_mask = BIT(0),
2444 .halt_reg = 0x3b68,
2446 .enable_reg = 0x3b68,
2447 .enable_mask = BIT(0),
2459 .halt_reg = 0x3b6c,
2461 .enable_reg = 0x3b6c,
2462 .enable_mask = BIT(0),
2474 .halt_reg = 0x3b74,
2476 .enable_reg = 0x3b74,
2477 .enable_mask = BIT(0),
2489 .halt_reg = 0x5024,
2491 .enable_reg = 0x5024,
2492 .enable_mask = BIT(0),
2504 .halt_reg = 0xe004,
2505 .hwcg_reg = 0xe004,
2508 .enable_reg = 0xe004,
2509 .enable_mask = BIT(0),
2521 .halt_reg = 0xe008,
2522 .hwcg_reg = 0xe008,
2525 .enable_reg = 0xe008,
2526 .enable_mask = BIT(0),
2537 .halt_reg = 0xf004,
2539 .enable_reg = 0xf004,
2540 .enable_mask = BIT(0),
2552 .halt_reg = 0xf064,
2554 .enable_reg = 0xf064,
2555 .enable_mask = BIT(0),
2567 .halt_reg = 0xf068,
2569 .enable_reg = 0xf068,
2570 .enable_mask = BIT(0),
2586 .gdscr = 0x1024,
2594 .gdscr = 0x1040,
2603 .gdscr = 0x1044,
2612 .gdscr = 0x2304,
2613 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2622 .gdscr = 0x34a0,
2623 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2624 0x35a8, 0x3868 },
2633 .gdscr = 0x3664,
2642 .gdscr = 0x3674,
2651 .gdscr = 0x36d4,
2660 .gdscr = 0xe020,
2661 .gds_hw_ctrl = 0xe024,
2831 [SPDM_BCR] = { 0x200 },
2832 [SPDM_RM_BCR] = { 0x300 },
2833 [MISC_BCR] = { 0x320 },
2834 [VIDEO_TOP_BCR] = { 0x1020 },
2835 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2836 [MDSS_BCR] = { 0x2300 },
2837 [THROTTLE_MDSS_BCR] = { 0x2460 },
2838 [CAMSS_PHY0_BCR] = { 0x3020 },
2839 [CAMSS_PHY1_BCR] = { 0x3050 },
2840 [CAMSS_PHY2_BCR] = { 0x3080 },
2841 [CAMSS_CSI0_BCR] = { 0x30b0 },
2842 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2843 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2844 [CAMSS_CSI1_BCR] = { 0x3120 },
2845 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2846 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2847 [CAMSS_CSI2_BCR] = { 0x3180 },
2848 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2849 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2850 [CAMSS_CSI3_BCR] = { 0x31e0 },
2851 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2852 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2853 [CAMSS_ISPIF_BCR] = { 0x3220 },
2854 [CAMSS_CCI_BCR] = { 0x3340 },
2855 [CAMSS_TOP_BCR] = { 0x3480 },
2856 [CAMSS_AHB_BCR] = { 0x3488 },
2857 [CAMSS_MICRO_BCR] = { 0x3490 },
2858 [CAMSS_JPEG_BCR] = { 0x35a0 },
2859 [CAMSS_VFE0_BCR] = { 0x3660 },
2860 [CAMSS_VFE1_BCR] = { 0x3670 },
2861 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2862 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2863 [CAMSS_CPP_BCR] = { 0x36d0 },
2864 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2865 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2866 [CAMSS_FD_BCR] = { 0x3b60 },
2867 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2868 [MNOCAHB_BCR] = { 0x5020 },
2869 [MNOCAXI_BCR] = { 0xd020 },
2870 [BMIC_SMMU_BCR] = { 0xe000 },
2871 [MNOC_MAXI_BCR] = { 0xf000 },
2872 [VMEM_BCR] = { 0xf060 },
2873 [BTO_BCR] = { 0x10004 },
2880 .max_register = 0x10004,