Lines Matching +full:0 +full:x3b00
49 { P_XO, 0 },
59 { P_XO, 0 },
71 { P_XO, 0 },
83 { P_XO, 0 },
95 { P_XO, 0 },
109 { P_XO, 0 },
125 { P_XO, 0 },
141 { P_XO, 0 },
157 { P_XO, 0 },
173 { P_XO, 0 },
191 { P_XO, 0 },
211 { P_XO, 0 },
245 { 1500000000, 2000000000, 0 },
251 { 1500000000, 2000000000, 0 },
255 { 500000000, 1500000000, 0 },
259 .offset = 0x0,
264 .enable_reg = 0x100,
265 .enable_mask = BIT(0),
276 .offset = 0x0,
289 .offset = 0x30,
294 .enable_reg = 0x100,
306 .offset = 0x30,
319 .offset = 0x4100,
332 .offset = 0x4100,
345 .offset = 0x60,
358 .offset = 0x60,
371 .offset = 0x90,
384 .offset = 0x90,
397 .offset = 0xc0,
410 .offset = 0xc0,
423 .offset = 0x4130,
436 .offset = 0x4130,
449 .offset = 0x4200,
462 .offset = 0x4200,
475 F(19200000, P_XO, 1, 0, 0),
476 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
477 F(80000000, P_MMPLL0, 10, 0, 0),
482 .cmd_rcgr = 0x5000,
495 F(19200000, P_XO, 1, 0, 0),
496 F(75000000, P_GPLL0_DIV, 4, 0, 0),
497 F(100000000, P_GPLL0, 6, 0, 0),
498 F(171430000, P_GPLL0, 3.5, 0, 0),
499 F(200000000, P_GPLL0, 3, 0, 0),
500 F(320000000, P_MMPLL0, 2.5, 0, 0),
501 F(400000000, P_MMPLL0, 2, 0, 0),
506 .cmd_rcgr = 0x5040,
519 .cmd_rcgr = 0x5090,
533 .cmd_rcgr = 0x4000,
552 F(19200000, P_XO, 1, 0, 0),
557 .cmd_rcgr = 0x4090,
570 .cmd_rcgr = 0x4010,
582 F(19200000, P_XO, 1, 0, 0),
583 F(50000000, P_GPLL0, 12, 0, 0),
588 .cmd_rcgr = 0x4060,
601 F(75000000, P_GPLL0_DIV, 4, 0, 0),
602 F(150000000, P_GPLL0, 4, 0, 0),
603 F(346666667, P_MMPLL3, 3, 0, 0),
604 F(520000000, P_MMPLL3, 2, 0, 0),
609 .cmd_rcgr = 0x1000,
623 .cmd_rcgr = 0x1060,
637 .cmd_rcgr = 0x1080,
651 .cmd_rcgr = 0x2000,
665 .cmd_rcgr = 0x2020,
679 F(85714286, P_GPLL0, 7, 0, 0),
680 F(100000000, P_GPLL0, 6, 0, 0),
681 F(150000000, P_GPLL0, 4, 0, 0),
682 F(171428571, P_GPLL0, 3.5, 0, 0),
683 F(200000000, P_GPLL0, 3, 0, 0),
684 F(275000000, P_MMPLL5, 3, 0, 0),
685 F(300000000, P_GPLL0, 2, 0, 0),
686 F(330000000, P_MMPLL5, 2.5, 0, 0),
687 F(412500000, P_MMPLL5, 2, 0, 0),
692 .cmd_rcgr = 0x2040,
710 .cmd_rcgr = 0x2060,
724 F(19200000, P_XO, 1, 0, 0),
729 .cmd_rcgr = 0x2080,
742 F(19200000, P_XO, 1, 0, 0),
747 .cmd_rcgr = 0x2100,
760 .cmd_rcgr = 0x2120,
773 .cmd_rcgr = 0x2140,
786 F(19200000, P_XO, 1, 0, 0),
791 .cmd_rcgr = 0x2160,
804 .cmd_rcgr = 0x2180,
827 .cmd_rcgr = 0x3420,
841 .cmd_rcgr = 0x3450,
855 F(4800000, P_XO, 4, 0, 0),
858 F(9600000, P_XO, 2, 0, 0),
860 F(19200000, P_XO, 1, 0, 0),
869 .cmd_rcgr = 0x3360,
883 .cmd_rcgr = 0x3390,
897 .cmd_rcgr = 0x33c0,
911 .cmd_rcgr = 0x33f0,
925 F(19200000, P_XO, 1, 0, 0),
926 F(37500000, P_GPLL0, 16, 0, 0),
927 F(50000000, P_GPLL0, 12, 0, 0),
928 F(100000000, P_GPLL0, 6, 0, 0),
933 .cmd_rcgr = 0x3300,
947 F(100000000, P_GPLL0_DIV, 3, 0, 0),
948 F(200000000, P_GPLL0, 3, 0, 0),
949 F(266666667, P_MMPLL0, 3, 0, 0),
954 .cmd_rcgr = 0x3000,
967 .cmd_rcgr = 0x3030,
980 .cmd_rcgr = 0x3060,
993 F(100000000, P_GPLL0_DIV, 3, 0, 0),
994 F(200000000, P_GPLL0, 3, 0, 0),
995 F(320000000, P_MMPLL4, 3, 0, 0),
996 F(384000000, P_MMPLL4, 2.5, 0, 0),
1001 .cmd_rcgr = 0x3240,
1014 .cmd_rcgr = 0x3260,
1027 .cmd_rcgr = 0x3280,
1040 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1041 F(150000000, P_GPLL0, 4, 0, 0),
1042 F(228571429, P_MMPLL0, 3.5, 0, 0),
1043 F(266666667, P_MMPLL0, 3, 0, 0),
1044 F(320000000, P_MMPLL0, 2.5, 0, 0),
1045 F(480000000, P_MMPLL4, 2, 0, 0),
1050 .cmd_rcgr = 0x3500,
1063 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1064 F(150000000, P_GPLL0, 4, 0, 0),
1065 F(228571429, P_MMPLL0, 3.5, 0, 0),
1066 F(266666667, P_MMPLL0, 3, 0, 0),
1067 F(320000000, P_MMPLL0, 2.5, 0, 0),
1072 .cmd_rcgr = 0x3540,
1085 .cmd_rcgr = 0x3560,
1098 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1099 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1100 F(300000000, P_GPLL0, 2, 0, 0),
1101 F(320000000, P_MMPLL0, 2.5, 0, 0),
1102 F(480000000, P_MMPLL4, 2, 0, 0),
1103 F(600000000, P_GPLL0, 1, 0, 0),
1108 .cmd_rcgr = 0x3600,
1121 .cmd_rcgr = 0x3620,
1134 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1135 F(200000000, P_GPLL0, 3, 0, 0),
1136 F(320000000, P_MMPLL0, 2.5, 0, 0),
1137 F(480000000, P_MMPLL4, 2, 0, 0),
1138 F(640000000, P_MMPLL4, 1.5, 0, 0),
1143 .cmd_rcgr = 0x3640,
1156 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1157 F(200000000, P_GPLL0, 3, 0, 0),
1158 F(266666667, P_MMPLL0, 3, 0, 0),
1159 F(480000000, P_MMPLL4, 2, 0, 0),
1160 F(600000000, P_GPLL0, 1, 0, 0),
1165 .cmd_rcgr = 0x3090,
1178 .cmd_rcgr = 0x3100,
1191 .cmd_rcgr = 0x3160,
1204 .cmd_rcgr = 0x31c0,
1217 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1218 F(200000000, P_GPLL0, 3, 0, 0),
1219 F(400000000, P_MMPLL0, 2, 0, 0),
1224 .cmd_rcgr = 0x3b00,
1237 .halt_reg = 0x5024,
1239 .enable_reg = 0x5024,
1240 .enable_mask = BIT(0),
1252 .halt_reg = 0x5054,
1254 .enable_reg = 0x5054,
1255 .enable_mask = BIT(0),
1267 .halt_reg = 0x5018,
1269 .enable_reg = 0x5018,
1270 .enable_mask = BIT(0),
1282 .halt_reg = 0x5014,
1284 .enable_reg = 0x5014,
1285 .enable_mask = BIT(0),
1296 .halt_reg = 0x5074,
1298 .enable_reg = 0x5074,
1299 .enable_mask = BIT(0),
1311 .halt_reg = 0x3c44,
1313 .enable_reg = 0x3c44,
1314 .enable_mask = BIT(0),
1326 .halt_reg = 0x3c48,
1328 .enable_reg = 0x3c48,
1329 .enable_mask = BIT(0),
1341 .halt_reg = 0x3c04,
1343 .enable_reg = 0x3c04,
1344 .enable_mask = BIT(0),
1356 .halt_reg = 0x3c08,
1358 .enable_reg = 0x3c08,
1359 .enable_mask = BIT(0),
1371 .halt_reg = 0x3c14,
1373 .enable_reg = 0x3c14,
1374 .enable_mask = BIT(0),
1386 .halt_reg = 0x3c18,
1388 .enable_reg = 0x3c18,
1389 .enable_mask = BIT(0),
1401 .halt_reg = 0x3c24,
1403 .enable_reg = 0x3c24,
1404 .enable_mask = BIT(0),
1416 .halt_reg = 0x3c28,
1418 .enable_reg = 0x3c28,
1419 .enable_mask = BIT(0),
1431 .halt_reg = 0x2474,
1433 .enable_reg = 0x2474,
1434 .enable_mask = BIT(0),
1446 .halt_reg = 0x2478,
1448 .enable_reg = 0x2478,
1449 .enable_mask = BIT(0),
1461 .halt_reg = 0x2444,
1463 .enable_reg = 0x2444,
1464 .enable_mask = BIT(0),
1476 .halt_reg = 0x2448,
1478 .enable_reg = 0x2448,
1479 .enable_mask = BIT(0),
1491 .halt_reg = 0x2454,
1493 .enable_reg = 0x2454,
1494 .enable_mask = BIT(0),
1506 .halt_reg = 0x2458,
1508 .enable_reg = 0x2458,
1509 .enable_mask = BIT(0),
1521 .halt_reg = 0x1194,
1523 .enable_reg = 0x1194,
1524 .enable_mask = BIT(0),
1536 .halt_reg = 0x1198,
1538 .enable_reg = 0x1198,
1539 .enable_mask = BIT(0),
1551 .halt_reg = 0x1174,
1553 .enable_reg = 0x1174,
1554 .enable_mask = BIT(0),
1566 .halt_reg = 0x1178,
1568 .enable_reg = 0x1178,
1569 .enable_mask = BIT(0),
1581 .halt_reg = 0x5298,
1583 .enable_reg = 0x5298,
1584 .enable_mask = BIT(0),
1596 .halt_reg = 0x4028,
1598 .enable_reg = 0x4028,
1599 .enable_mask = BIT(0),
1611 .halt_reg = 0x40b0,
1613 .enable_reg = 0x40b0,
1614 .enable_mask = BIT(0),
1626 .halt_reg = 0x403c,
1628 .enable_reg = 0x403c,
1629 .enable_mask = BIT(0),
1641 .halt_reg = 0x4044,
1643 .enable_reg = 0x4044,
1644 .enable_mask = BIT(0),
1656 .halt_reg = 0x1204,
1658 .enable_reg = 0x1204,
1659 .enable_mask = BIT(0),
1671 .halt_reg = 0x1208,
1673 .enable_reg = 0x1208,
1674 .enable_mask = BIT(0),
1686 .halt_reg = 0x4084,
1688 .enable_reg = 0x4084,
1689 .enable_mask = BIT(0),
1701 .halt_reg = 0x4088,
1703 .enable_reg = 0x4088,
1704 .enable_mask = BIT(0),
1716 .halt_reg = 0x1028,
1718 .enable_reg = 0x1028,
1719 .enable_mask = BIT(0),
1731 .halt_reg = 0x1034,
1733 .enable_reg = 0x1034,
1734 .enable_mask = BIT(0),
1746 .halt_reg = 0x1038,
1748 .enable_reg = 0x1038,
1749 .enable_mask = BIT(0),
1761 .halt_reg = 0x1030,
1763 .enable_reg = 0x1030,
1764 .enable_mask = BIT(0),
1776 .halt_reg = 0x1048,
1778 .enable_reg = 0x1048,
1779 .enable_mask = BIT(0),
1791 .halt_reg = 0x104c,
1793 .enable_reg = 0x104c,
1794 .enable_mask = BIT(0),
1806 .halt_reg = 0x2308,
1808 .enable_reg = 0x2308,
1809 .enable_mask = BIT(0),
1821 .halt_reg = 0x230c,
1823 .enable_reg = 0x230c,
1824 .enable_mask = BIT(0),
1836 .halt_reg = 0x2310,
1838 .enable_reg = 0x2310,
1839 .enable_mask = BIT(0),
1851 .halt_reg = 0x2314,
1853 .enable_reg = 0x2314,
1854 .enable_mask = BIT(0),
1866 .halt_reg = 0x2318,
1868 .enable_reg = 0x2318,
1869 .enable_mask = BIT(0),
1881 .halt_reg = 0x231c,
1883 .enable_reg = 0x231c,
1884 .enable_mask = BIT(0),
1896 .halt_reg = 0x2324,
1898 .enable_reg = 0x2324,
1899 .enable_mask = BIT(0),
1911 .halt_reg = 0x2328,
1913 .enable_reg = 0x2328,
1914 .enable_mask = BIT(0),
1926 .halt_reg = 0x2338,
1928 .enable_reg = 0x2338,
1929 .enable_mask = BIT(0),
1941 .halt_reg = 0x233c,
1943 .enable_reg = 0x233c,
1944 .enable_mask = BIT(0),
1956 .halt_reg = 0x2340,
1958 .enable_reg = 0x2340,
1959 .enable_mask = BIT(0),
1971 .halt_reg = 0x2344,
1973 .enable_reg = 0x2344,
1974 .enable_mask = BIT(0),
1986 .halt_reg = 0x2348,
1988 .enable_reg = 0x2348,
1989 .enable_mask = BIT(0),
2001 .halt_reg = 0x3484,
2003 .enable_reg = 0x3484,
2004 .enable_mask = BIT(0),
2016 .halt_reg = 0x348c,
2018 .enable_reg = 0x348c,
2019 .enable_mask = BIT(0),
2031 .halt_reg = 0x3494,
2033 .enable_reg = 0x3494,
2034 .enable_mask = BIT(0),
2046 .halt_reg = 0x3444,
2048 .enable_reg = 0x3444,
2049 .enable_mask = BIT(0),
2061 .halt_reg = 0x3474,
2063 .enable_reg = 0x3474,
2064 .enable_mask = BIT(0),
2076 .halt_reg = 0x3384,
2078 .enable_reg = 0x3384,
2079 .enable_mask = BIT(0),
2091 .halt_reg = 0x33b4,
2093 .enable_reg = 0x33b4,
2094 .enable_mask = BIT(0),
2106 .halt_reg = 0x33e4,
2108 .enable_reg = 0x33e4,
2109 .enable_mask = BIT(0),
2121 .halt_reg = 0x3414,
2123 .enable_reg = 0x3414,
2124 .enable_mask = BIT(0),
2136 .halt_reg = 0x3344,
2138 .enable_reg = 0x3344,
2139 .enable_mask = BIT(0),
2151 .halt_reg = 0x3348,
2153 .enable_reg = 0x3348,
2154 .enable_mask = BIT(0),
2166 .halt_reg = 0x3024,
2168 .enable_reg = 0x3024,
2169 .enable_mask = BIT(0),
2181 .halt_reg = 0x3054,
2183 .enable_reg = 0x3054,
2184 .enable_mask = BIT(0),
2196 .halt_reg = 0x3084,
2198 .enable_reg = 0x3084,
2199 .enable_mask = BIT(0),
2211 .halt_reg = 0x3234,
2213 .enable_reg = 0x3234,
2214 .enable_mask = BIT(0),
2226 .halt_reg = 0x3254,
2228 .enable_reg = 0x3254,
2229 .enable_mask = BIT(0),
2241 .halt_reg = 0x3274,
2243 .enable_reg = 0x3274,
2244 .enable_mask = BIT(0),
2256 .halt_reg = 0x35a8,
2258 .enable_reg = 0x35a8,
2259 .enable_mask = BIT(0),
2271 .halt_reg = 0x35b0,
2273 .enable_reg = 0x35b0,
2274 .enable_mask = BIT(0),
2286 .halt_reg = 0x35c0,
2288 .enable_reg = 0x35c0,
2289 .enable_mask = BIT(0),
2301 .halt_reg = 0x35b4,
2303 .enable_reg = 0x35b4,
2304 .enable_mask = BIT(0),
2316 .halt_reg = 0x35b8,
2318 .enable_reg = 0x35b8,
2319 .enable_mask = BIT(0),
2331 .halt_reg = 0x36b8,
2333 .enable_reg = 0x36b8,
2334 .enable_mask = BIT(0),
2346 .halt_reg = 0x36bc,
2348 .enable_reg = 0x36bc,
2349 .enable_mask = BIT(0),
2361 .halt_reg = 0x36a8,
2363 .enable_reg = 0x36a8,
2364 .enable_mask = BIT(0),
2376 .halt_reg = 0x3720,
2378 .enable_reg = 0x3720,
2379 .enable_mask = BIT(0),
2391 .halt_reg = 0x3668,
2393 .enable_reg = 0x3668,
2394 .enable_mask = BIT(0),
2406 .halt_reg = 0x36ac,
2408 .enable_reg = 0x36ac,
2409 .enable_mask = BIT(0),
2421 .halt_reg = 0x3724,
2423 .enable_reg = 0x3724,
2424 .enable_mask = BIT(0),
2436 .halt_reg = 0x3678,
2438 .enable_reg = 0x3678,
2439 .enable_mask = BIT(0),
2451 .halt_reg = 0x3704,
2453 .enable_reg = 0x3704,
2454 .enable_mask = BIT(0),
2466 .halt_reg = 0x3714,
2468 .enable_reg = 0x3714,
2469 .enable_mask = BIT(0),
2481 .halt_reg = 0x36c8,
2483 .enable_reg = 0x36c8,
2484 .enable_mask = BIT(0),
2496 .halt_reg = 0x36c4,
2498 .enable_reg = 0x36c4,
2499 .enable_mask = BIT(0),
2511 .halt_reg = 0x36b0,
2513 .enable_reg = 0x36b0,
2514 .enable_mask = BIT(0),
2526 .halt_reg = 0x36b4,
2528 .enable_reg = 0x36b4,
2529 .enable_mask = BIT(0),
2541 .halt_reg = 0x30b4,
2543 .enable_reg = 0x30b4,
2544 .enable_mask = BIT(0),
2556 .halt_reg = 0x30bc,
2558 .enable_reg = 0x30bc,
2559 .enable_mask = BIT(0),
2571 .halt_reg = 0x30c4,
2573 .enable_reg = 0x30c4,
2574 .enable_mask = BIT(0),
2586 .halt_reg = 0x30d4,
2588 .enable_reg = 0x30d4,
2589 .enable_mask = BIT(0),
2601 .halt_reg = 0x30e4,
2603 .enable_reg = 0x30e4,
2604 .enable_mask = BIT(0),
2616 .halt_reg = 0x3124,
2618 .enable_reg = 0x3124,
2619 .enable_mask = BIT(0),
2631 .halt_reg = 0x3128,
2633 .enable_reg = 0x3128,
2634 .enable_mask = BIT(0),
2646 .halt_reg = 0x3134,
2648 .enable_reg = 0x3134,
2649 .enable_mask = BIT(0),
2661 .halt_reg = 0x3144,
2663 .enable_reg = 0x3144,
2664 .enable_mask = BIT(0),
2676 .halt_reg = 0x3154,
2678 .enable_reg = 0x3154,
2679 .enable_mask = BIT(0),
2691 .halt_reg = 0x3184,
2693 .enable_reg = 0x3184,
2694 .enable_mask = BIT(0),
2706 .halt_reg = 0x3188,
2708 .enable_reg = 0x3188,
2709 .enable_mask = BIT(0),
2721 .halt_reg = 0x3194,
2723 .enable_reg = 0x3194,
2724 .enable_mask = BIT(0),
2736 .halt_reg = 0x31a4,
2738 .enable_reg = 0x31a4,
2739 .enable_mask = BIT(0),
2751 .halt_reg = 0x31b4,
2753 .enable_reg = 0x31b4,
2754 .enable_mask = BIT(0),
2766 .halt_reg = 0x31e4,
2768 .enable_reg = 0x31e4,
2769 .enable_mask = BIT(0),
2781 .halt_reg = 0x31e8,
2783 .enable_reg = 0x31e8,
2784 .enable_mask = BIT(0),
2796 .halt_reg = 0x31f4,
2798 .enable_reg = 0x31f4,
2799 .enable_mask = BIT(0),
2811 .halt_reg = 0x3204,
2813 .enable_reg = 0x3204,
2814 .enable_mask = BIT(0),
2826 .halt_reg = 0x3214,
2828 .enable_reg = 0x3214,
2829 .enable_mask = BIT(0),
2841 .halt_reg = 0x3224,
2843 .enable_reg = 0x3224,
2844 .enable_mask = BIT(0),
2856 .halt_reg = 0x3b68,
2858 .enable_reg = 0x3b68,
2859 .enable_mask = BIT(0),
2871 .halt_reg = 0x3b6c,
2873 .enable_reg = 0x3b6c,
2874 .enable_mask = BIT(0),
2886 .halt_reg = 0x3ba74,
2888 .enable_reg = 0x3ba74,
2889 .enable_mask = BIT(0),
2905 .gdscr = 0x529c,
2914 .gdscr = 0x119c,
2915 .gds_hw_ctrl = 0x120c,
2924 .gdscr = 0x247c,
2925 .gds_hw_ctrl = 0x2480,
2934 .gdscr = 0x3c4c,
2935 .gds_hw_ctrl = 0x3c50,
2944 .gdscr = 0x1024,
2945 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2955 .gdscr = 0x1040,
2956 .cxcs = (unsigned int []){ 0x1048 },
2967 .gdscr = 0x1044,
2968 .cxcs = (unsigned int []){ 0x104c },
2979 .gdscr = 0x34a0,
2980 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
2990 .gdscr = 0x3664,
2991 .cxcs = (unsigned int []){ 0x36a8 },
3001 .gdscr = 0x3674,
3002 .cxcs = (unsigned int []){ 0x36ac },
3012 .gdscr = 0x35a4,
3013 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3023 .gdscr = 0x36d4,
3024 .cxcs = (unsigned int []){ 0x36b0 },
3034 .gdscr = 0x3b64,
3035 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3045 .gdscr = 0x2304,
3046 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3056 .gdscr = 0x4034,
3057 .gds_hw_ctrl = 0x4038,
3066 .gdscr = 0x4024,
3067 .clamp_io_ctrl = 0x4300,
3068 .cxcs = (unsigned int []){ 0x4028 },
3273 [MMAGICAHB_BCR] = { 0x5020 },
3274 [MMAGIC_CFG_BCR] = { 0x5050 },
3275 [MISC_BCR] = { 0x5010 },
3276 [BTO_BCR] = { 0x5030 },
3277 [MMAGICAXI_BCR] = { 0x5060 },
3278 [MMAGICMAXI_BCR] = { 0x5070 },
3279 [DSA_BCR] = { 0x50a0 },
3280 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3281 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3282 [SMMU_VFE_BCR] = { 0x3c00 },
3283 [SMMU_CPP_BCR] = { 0x3c10 },
3284 [SMMU_JPEG_BCR] = { 0x3c20 },
3285 [MMAGIC_MDSS_BCR] = { 0x2470 },
3286 [THROTTLE_MDSS_BCR] = { 0x2460 },
3287 [SMMU_ROT_BCR] = { 0x2440 },
3288 [SMMU_MDP_BCR] = { 0x2450 },
3289 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3290 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3291 [SMMU_VIDEO_BCR] = { 0x1170 },
3292 [MMAGIC_BIMC_BCR] = { 0x5290 },
3293 [GPU_GX_BCR] = { 0x4020 },
3294 [GPU_BCR] = { 0x4030 },
3295 [GPU_AON_BCR] = { 0x4040 },
3296 [VMEM_BCR] = { 0x1200 },
3297 [MMSS_RBCPR_BCR] = { 0x4080 },
3298 [VIDEO_BCR] = { 0x1020 },
3299 [MDSS_BCR] = { 0x2300 },
3300 [CAMSS_TOP_BCR] = { 0x3480 },
3301 [CAMSS_AHB_BCR] = { 0x3488 },
3302 [CAMSS_MICRO_BCR] = { 0x3490 },
3303 [CAMSS_CCI_BCR] = { 0x3340 },
3304 [CAMSS_PHY0_BCR] = { 0x3020 },
3305 [CAMSS_PHY1_BCR] = { 0x3050 },
3306 [CAMSS_PHY2_BCR] = { 0x3080 },
3307 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3308 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3309 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3310 [CAMSS_JPEG_BCR] = { 0x35a0 },
3311 [CAMSS_VFE_BCR] = { 0x36a0 },
3312 [CAMSS_VFE0_BCR] = { 0x3660 },
3313 [CAMSS_VFE1_BCR] = { 0x3670 },
3314 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3315 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3316 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3317 [CAMSS_CPP_BCR] = { 0x36d0 },
3318 [CAMSS_CSI0_BCR] = { 0x30b0 },
3319 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3320 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3321 [CAMSS_CSI1_BCR] = { 0x3120 },
3322 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3323 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3324 [CAMSS_CSI2_BCR] = { 0x3180 },
3325 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3326 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3327 [CAMSS_CSI3_BCR] = { 0x31e0 },
3328 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3329 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3330 [CAMSS_ISPIF_BCR] = { 0x3220 },
3331 [FD_BCR] = { 0x3b60 },
3332 [MMSS_SPDM_RM_BCR] = { 0x300 },
3339 .max_register = 0xb008,
3370 regmap_update_bits(regmap, 0x50d8, BIT(31), 0); in mmcc_msm8996_probe()
3372 regmap_update_bits(regmap, 0x5054, BIT(15), 0); in mmcc_msm8996_probe()