Lines Matching +full:0 +full:x4084
43 { P_XO, 0 },
57 { P_XO, 0 },
75 { P_XO, 0 },
91 { P_XO, 0 },
107 { P_XO, 0 },
125 { P_XO, 0 },
143 { P_XO, 0 },
161 { P_XO, 0 },
177 { P_XO, 0 },
195 { P_XO, 0 },
215 .l_reg = 0x0004,
216 .m_reg = 0x0008,
217 .n_reg = 0x000c,
218 .config_reg = 0x0014,
219 .mode_reg = 0x0000,
220 .status_reg = 0x001c,
231 .enable_reg = 0x0100,
232 .enable_mask = BIT(0),
242 .l_reg = 0x0044,
243 .m_reg = 0x0048,
244 .n_reg = 0x004c,
245 .config_reg = 0x0050,
246 .mode_reg = 0x0040,
247 .status_reg = 0x005c,
258 .enable_reg = 0x0100,
269 .l_reg = 0x4104,
270 .m_reg = 0x4108,
271 .n_reg = 0x410c,
272 .config_reg = 0x4110,
273 .mode_reg = 0x4100,
274 .status_reg = 0x411c,
284 .l_reg = 0x0084,
285 .m_reg = 0x0088,
286 .n_reg = 0x008c,
287 .config_reg = 0x0090,
288 .mode_reg = 0x0080,
289 .status_reg = 0x009c,
300 .l_reg = 0x00a4,
301 .m_reg = 0x00a8,
302 .n_reg = 0x00ac,
303 .config_reg = 0x00b0,
304 .mode_reg = 0x0080,
305 .status_reg = 0x00bc,
315 .cmd_rcgr = 0x5000,
327 F(19200000, P_XO, 1, 0, 0),
328 F(37500000, P_GPLL0, 16, 0, 0),
329 F(50000000, P_GPLL0, 12, 0, 0),
330 F(75000000, P_GPLL0, 8, 0, 0),
331 F(100000000, P_GPLL0, 6, 0, 0),
332 F(150000000, P_GPLL0, 4, 0, 0),
333 F(333430000, P_MMPLL1, 3.5, 0, 0),
334 F(400000000, P_MMPLL0, 2, 0, 0),
335 F(466800000, P_MMPLL1, 2.5, 0, 0),
339 .cmd_rcgr = 0x5040,
352 F(19200000, P_XO, 1, 0, 0),
353 F(37500000, P_GPLL0, 16, 0, 0),
354 F(50000000, P_GPLL0, 12, 0, 0),
355 F(75000000, P_GPLL0, 8, 0, 0),
356 F(109090000, P_GPLL0, 5.5, 0, 0),
357 F(150000000, P_GPLL0, 4, 0, 0),
358 F(228570000, P_MMPLL0, 3.5, 0, 0),
359 F(320000000, P_MMPLL0, 2.5, 0, 0),
363 .cmd_rcgr = 0x5090,
376 F(100000000, P_GPLL0, 6, 0, 0),
377 F(200000000, P_MMPLL0, 4, 0, 0),
382 .cmd_rcgr = 0x3090,
395 .cmd_rcgr = 0x3100,
408 .cmd_rcgr = 0x3160,
421 .cmd_rcgr = 0x31c0,
434 F(37500000, P_GPLL0, 16, 0, 0),
435 F(50000000, P_GPLL0, 12, 0, 0),
436 F(60000000, P_GPLL0, 10, 0, 0),
437 F(80000000, P_GPLL0, 7.5, 0, 0),
438 F(100000000, P_GPLL0, 6, 0, 0),
439 F(109090000, P_GPLL0, 5.5, 0, 0),
440 F(133330000, P_GPLL0, 4.5, 0, 0),
441 F(200000000, P_GPLL0, 3, 0, 0),
442 F(228570000, P_MMPLL0, 3.5, 0, 0),
443 F(266670000, P_MMPLL0, 3, 0, 0),
444 F(320000000, P_MMPLL0, 2.5, 0, 0),
445 F(465000000, P_MMPLL4, 2, 0, 0),
446 F(600000000, P_GPLL0, 1, 0, 0),
451 .cmd_rcgr = 0x3600,
464 .cmd_rcgr = 0x3620,
477 F(37500000, P_GPLL0, 16, 0, 0),
478 F(60000000, P_GPLL0, 10, 0, 0),
479 F(75000000, P_GPLL0, 8, 0, 0),
480 F(85710000, P_GPLL0, 7, 0, 0),
481 F(100000000, P_GPLL0, 6, 0, 0),
482 F(150000000, P_GPLL0, 4, 0, 0),
483 F(160000000, P_MMPLL0, 5, 0, 0),
484 F(200000000, P_MMPLL0, 4, 0, 0),
485 F(228570000, P_MMPLL0, 3.5, 0, 0),
486 F(300000000, P_GPLL0, 2, 0, 0),
487 F(320000000, P_MMPLL0, 2.5, 0, 0),
492 .cmd_rcgr = 0x2040,
505 .cmd_rcgr = 0x4000,
517 F(75000000, P_GPLL0, 8, 0, 0),
518 F(133330000, P_GPLL0, 4.5, 0, 0),
519 F(200000000, P_GPLL0, 3, 0, 0),
520 F(228570000, P_MMPLL0, 3.5, 0, 0),
521 F(266670000, P_MMPLL0, 3, 0, 0),
522 F(320000000, P_MMPLL0, 2.5, 0, 0),
527 .cmd_rcgr = 0x3500,
540 .cmd_rcgr = 0x3520,
553 .cmd_rcgr = 0x3540,
566 .cmd_rcgr = 0x2000,
580 .cmd_rcgr = 0x2020,
594 F(50000000, P_GPLL0, 12, 0, 0),
595 F(100000000, P_GPLL0, 6, 0, 0),
596 F(133330000, P_GPLL0, 4.5, 0, 0),
597 F(200000000, P_MMPLL0, 4, 0, 0),
598 F(266670000, P_MMPLL0, 3, 0, 0),
599 F(465000000, P_MMPLL3, 2, 0, 0),
604 .cmd_rcgr = 0x1000,
618 F(150000000, P_GPLL0, 4, 0, 0),
619 F(320000000, P_MMPLL0, 2.5, 0, 0),
624 .cmd_rcgr = 0x2430,
637 F(19200000, P_XO, 1, 0, 0),
642 .cmd_rcgr = 0x3300,
666 .cmd_rcgr = 0x3420,
680 .cmd_rcgr = 0x3450,
694 F(4800000, P_XO, 4, 0, 0),
697 F(9600000, P_XO, 2, 0, 0),
699 F(19200000, P_XO, 1, 0, 0),
702 F(48000000, P_GPLL0, 12.5, 0, 0),
703 F(64000000, P_MMPLL0, 12.5, 0, 0),
708 .cmd_rcgr = 0x3360,
722 .cmd_rcgr = 0x3390,
736 .cmd_rcgr = 0x33c0,
750 .cmd_rcgr = 0x33f0,
764 F(100000000, P_GPLL0, 6, 0, 0),
765 F(200000000, P_MMPLL0, 4, 0, 0),
770 .cmd_rcgr = 0x3000,
783 .cmd_rcgr = 0x3030,
796 .cmd_rcgr = 0x3060,
809 F(133330000, P_GPLL0, 4.5, 0, 0),
810 F(266670000, P_MMPLL0, 3, 0, 0),
811 F(320000000, P_MMPLL0, 2.5, 0, 0),
812 F(372000000, P_MMPLL4, 2.5, 0, 0),
813 F(465000000, P_MMPLL4, 2, 0, 0),
814 F(600000000, P_GPLL0, 1, 0, 0),
819 .cmd_rcgr = 0x3640,
832 .cmd_rcgr = 0x2120,
845 .cmd_rcgr = 0x2140,
858 F(19200000, P_XO, 1, 0, 0),
863 .cmd_rcgr = 0x20e0,
876 F(135000000, P_EDPLINK, 2, 0, 0),
877 F(270000000, P_EDPLINK, 11, 0, 0),
882 .cmd_rcgr = 0x20c0,
901 .cmd_rcgr = 0x20a0,
915 F(19200000, P_XO, 1, 0, 0),
920 .cmd_rcgr = 0x2160,
933 .cmd_rcgr = 0x2180,
951 .cmd_rcgr = 0x2060,
965 F(19200000, P_XO, 1, 0, 0),
970 .cmd_rcgr = 0x2100,
983 F(19200000, P_XO, 1, 0, 0),
988 .cmd_rcgr = 0x2080,
1001 F(50000000, P_GPLL0, 12, 0, 0),
1006 .cmd_rcgr = 0x4060,
1019 F(19200000, P_XO, 1, 0, 0),
1024 .cmd_rcgr = 0x4090,
1037 F(50000000, P_GPLL0, 12, 0, 0),
1038 F(100000000, P_GPLL0, 6, 0, 0),
1039 F(133330000, P_GPLL0, 4.5, 0, 0),
1040 F(200000000, P_MMPLL0, 4, 0, 0),
1041 F(266670000, P_MMPLL0, 3, 0, 0),
1042 F(465000000, P_MMPLL3, 2, 0, 0),
1047 .cmd_rcgr = 0x1320,
1060 F(50000000, P_GPLL0, 12, 0, 0),
1061 F(100000000, P_GPLL0, 6, 0, 0),
1062 F(200000000, P_MMPLL0, 4, 0, 0),
1063 F(320000000, P_MMPLL0, 2.5, 0, 0),
1064 F(400000000, P_MMPLL0, 2, 0, 0),
1069 .cmd_rcgr = 0x1300,
1082 F(40000000, P_GPLL0, 15, 0, 0),
1083 F(80000000, P_MMPLL0, 10, 0, 0),
1088 .cmd_rcgr = 0x1340,
1101 .halt_reg = 0x5104,
1103 .enable_reg = 0x5104,
1104 .enable_mask = BIT(0),
1116 .halt_reg = 0x5100,
1118 .enable_reg = 0x5100,
1119 .enable_mask = BIT(0),
1133 .halt_reg = 0x2414,
1135 .enable_reg = 0x2414,
1136 .enable_mask = BIT(0),
1150 .halt_reg = 0x2418,
1152 .enable_reg = 0x2418,
1153 .enable_mask = BIT(0),
1167 .halt_reg = 0x2410,
1169 .enable_reg = 0x2410,
1170 .enable_mask = BIT(0),
1184 .halt_reg = 0x241c,
1186 .enable_reg = 0x241c,
1187 .enable_mask = BIT(0),
1201 .halt_reg = 0x2420,
1203 .enable_reg = 0x2420,
1204 .enable_mask = BIT(0),
1218 .halt_reg = 0x2404,
1220 .enable_reg = 0x2404,
1221 .enable_mask = BIT(0),
1235 .halt_reg = 0x348c,
1237 .enable_reg = 0x348c,
1238 .enable_mask = BIT(0),
1252 .halt_reg = 0x3348,
1254 .enable_reg = 0x3348,
1255 .enable_mask = BIT(0),
1268 .halt_reg = 0x3344,
1270 .enable_reg = 0x3344,
1271 .enable_mask = BIT(0),
1285 .halt_reg = 0x30bc,
1287 .enable_reg = 0x30bc,
1288 .enable_mask = BIT(0),
1301 .halt_reg = 0x30b4,
1303 .enable_reg = 0x30b4,
1304 .enable_mask = BIT(0),
1318 .halt_reg = 0x30c4,
1320 .enable_reg = 0x30c4,
1321 .enable_mask = BIT(0),
1335 .halt_reg = 0x30e4,
1337 .enable_reg = 0x30e4,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0x30d4,
1354 .enable_reg = 0x30d4,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x3128,
1371 .enable_reg = 0x3128,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x3124,
1388 .enable_reg = 0x3124,
1389 .enable_mask = BIT(0),
1403 .halt_reg = 0x3134,
1405 .enable_reg = 0x3134,
1406 .enable_mask = BIT(0),
1420 .halt_reg = 0x3154,
1422 .enable_reg = 0x3154,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x3144,
1439 .enable_reg = 0x3144,
1440 .enable_mask = BIT(0),
1454 .halt_reg = 0x3188,
1456 .enable_reg = 0x3188,
1457 .enable_mask = BIT(0),
1470 .halt_reg = 0x3184,
1472 .enable_reg = 0x3184,
1473 .enable_mask = BIT(0),
1487 .halt_reg = 0x3194,
1489 .enable_reg = 0x3194,
1490 .enable_mask = BIT(0),
1504 .halt_reg = 0x31b4,
1506 .enable_reg = 0x31b4,
1507 .enable_mask = BIT(0),
1521 .halt_reg = 0x31a4,
1523 .enable_reg = 0x31a4,
1524 .enable_mask = BIT(0),
1538 .halt_reg = 0x31e8,
1540 .enable_reg = 0x31e8,
1541 .enable_mask = BIT(0),
1554 .halt_reg = 0x31e4,
1556 .enable_reg = 0x31e4,
1557 .enable_mask = BIT(0),
1571 .halt_reg = 0x31f4,
1573 .enable_reg = 0x31f4,
1574 .enable_mask = BIT(0),
1588 .halt_reg = 0x3214,
1590 .enable_reg = 0x3214,
1591 .enable_mask = BIT(0),
1605 .halt_reg = 0x3204,
1607 .enable_reg = 0x3204,
1608 .enable_mask = BIT(0),
1622 .halt_reg = 0x3704,
1624 .enable_reg = 0x3704,
1625 .enable_mask = BIT(0),
1639 .halt_reg = 0x3714,
1641 .enable_reg = 0x3714,
1642 .enable_mask = BIT(0),
1656 .halt_reg = 0x3444,
1658 .enable_reg = 0x3444,
1659 .enable_mask = BIT(0),
1673 .halt_reg = 0x3474,
1675 .enable_reg = 0x3474,
1676 .enable_mask = BIT(0),
1690 .halt_reg = 0x3224,
1692 .enable_reg = 0x3224,
1693 .enable_mask = BIT(0),
1707 .halt_reg = 0x35a8,
1709 .enable_reg = 0x35a8,
1710 .enable_mask = BIT(0),
1724 .halt_reg = 0x35ac,
1726 .enable_reg = 0x35ac,
1727 .enable_mask = BIT(0),
1741 .halt_reg = 0x35b0,
1743 .enable_reg = 0x35b0,
1744 .enable_mask = BIT(0),
1758 .halt_reg = 0x35b4,
1760 .enable_reg = 0x35b4,
1761 .enable_mask = BIT(0),
1774 .halt_reg = 0x35b8,
1776 .enable_reg = 0x35b8,
1777 .enable_mask = BIT(0),
1790 .halt_reg = 0x3384,
1792 .enable_reg = 0x3384,
1793 .enable_mask = BIT(0),
1807 .halt_reg = 0x33b4,
1809 .enable_reg = 0x33b4,
1810 .enable_mask = BIT(0),
1824 .halt_reg = 0x33e4,
1826 .enable_reg = 0x33e4,
1827 .enable_mask = BIT(0),
1841 .halt_reg = 0x3414,
1843 .enable_reg = 0x3414,
1844 .enable_mask = BIT(0),
1858 .halt_reg = 0x3494,
1860 .enable_reg = 0x3494,
1861 .enable_mask = BIT(0),
1874 .halt_reg = 0x3024,
1876 .enable_reg = 0x3024,
1877 .enable_mask = BIT(0),
1891 .halt_reg = 0x3054,
1893 .enable_reg = 0x3054,
1894 .enable_mask = BIT(0),
1908 .halt_reg = 0x3084,
1910 .enable_reg = 0x3084,
1911 .enable_mask = BIT(0),
1925 .halt_reg = 0x3484,
1927 .enable_reg = 0x3484,
1928 .enable_mask = BIT(0),
1942 .halt_reg = 0x36b4,
1944 .enable_reg = 0x36b4,
1945 .enable_mask = BIT(0),
1959 .halt_reg = 0x36b0,
1961 .enable_reg = 0x36b0,
1962 .enable_mask = BIT(0),
1976 .halt_reg = 0x36a8,
1978 .enable_reg = 0x36a8,
1979 .enable_mask = BIT(0),
1993 .halt_reg = 0x36ac,
1995 .enable_reg = 0x36ac,
1996 .enable_mask = BIT(0),
2010 .halt_reg = 0x36b8,
2012 .enable_reg = 0x36b8,
2013 .enable_mask = BIT(0),
2027 .halt_reg = 0x36bc,
2029 .enable_reg = 0x36bc,
2030 .enable_mask = BIT(0),
2044 .halt_reg = 0x2308,
2046 .enable_reg = 0x2308,
2047 .enable_mask = BIT(0),
2061 .halt_reg = 0x2310,
2063 .enable_reg = 0x2310,
2064 .enable_mask = BIT(0),
2078 .halt_reg = 0x233c,
2080 .enable_reg = 0x233c,
2081 .enable_mask = BIT(0),
2095 .halt_reg = 0x2340,
2097 .enable_reg = 0x2340,
2098 .enable_mask = BIT(0),
2112 .halt_reg = 0x2334,
2114 .enable_reg = 0x2334,
2115 .enable_mask = BIT(0),
2129 .halt_reg = 0x2330,
2131 .enable_reg = 0x2330,
2132 .enable_mask = BIT(0),
2146 .halt_reg = 0x232c,
2148 .enable_reg = 0x232c,
2149 .enable_mask = BIT(0),
2163 .halt_reg = 0x2344,
2165 .enable_reg = 0x2344,
2166 .enable_mask = BIT(0),
2180 .halt_reg = 0x2348,
2182 .enable_reg = 0x2348,
2183 .enable_mask = BIT(0),
2197 .halt_reg = 0x2324,
2199 .enable_reg = 0x2324,
2200 .enable_mask = BIT(0),
2214 .halt_reg = 0x230c,
2216 .enable_reg = 0x230c,
2217 .enable_mask = BIT(0),
2231 .halt_reg = 0x2338,
2233 .enable_reg = 0x2338,
2234 .enable_mask = BIT(0),
2248 .halt_reg = 0x231c,
2250 .enable_reg = 0x231c,
2251 .enable_mask = BIT(0),
2265 .halt_reg = 0x2320,
2267 .enable_reg = 0x2320,
2268 .enable_mask = BIT(0),
2282 .halt_reg = 0x2314,
2284 .enable_reg = 0x2314,
2285 .enable_mask = BIT(0),
2299 .halt_reg = 0x2318,
2301 .enable_reg = 0x2318,
2302 .enable_mask = BIT(0),
2316 .halt_reg = 0x2328,
2318 .enable_reg = 0x2328,
2319 .enable_mask = BIT(0),
2333 .halt_reg = 0x4088,
2335 .enable_reg = 0x4088,
2336 .enable_mask = BIT(0),
2350 .halt_reg = 0x4084,
2352 .enable_reg = 0x4084,
2353 .enable_mask = BIT(0),
2367 .halt_reg = 0x0230,
2369 .enable_reg = 0x0230,
2370 .enable_mask = BIT(0),
2384 .halt_reg = 0x0210,
2386 .enable_reg = 0x0210,
2387 .enable_mask = BIT(0),
2401 .halt_reg = 0x023c,
2403 .enable_reg = 0x023c,
2404 .enable_mask = BIT(0),
2418 .halt_reg = 0x022c,
2420 .enable_reg = 0x022c,
2421 .enable_mask = BIT(0),
2435 .halt_reg = 0x0204,
2437 .enable_reg = 0x0204,
2438 .enable_mask = BIT(0),
2452 .halt_reg = 0x0208,
2454 .enable_reg = 0x0208,
2455 .enable_mask = BIT(0),
2469 .halt_reg = 0x0224,
2471 .enable_reg = 0x0224,
2472 .enable_mask = BIT(0),
2486 .halt_reg = 0x020c,
2488 .enable_reg = 0x020c,
2489 .enable_mask = BIT(0),
2503 .halt_reg = 0x0234,
2505 .enable_reg = 0x0234,
2506 .enable_mask = BIT(0),
2520 .halt_reg = 0x0228,
2522 .enable_reg = 0x0228,
2523 .enable_mask = BIT(0),
2537 .halt_reg = 0x0214,
2539 .enable_reg = 0x0214,
2540 .enable_mask = BIT(0),
2554 .halt_reg = 0x0218,
2556 .enable_reg = 0x0218,
2557 .enable_mask = BIT(0),
2571 .halt_reg = 0x021c,
2573 .enable_reg = 0x021c,
2574 .enable_mask = BIT(0),
2588 .halt_reg = 0x0304,
2590 .enable_reg = 0x0304,
2591 .enable_mask = BIT(0),
2605 .halt_reg = 0x0308,
2607 .enable_reg = 0x0308,
2608 .enable_mask = BIT(0),
2623 .halt_reg = 0x502c,
2625 .enable_reg = 0x502c,
2626 .enable_mask = BIT(0),
2640 .halt_reg = 0x5024,
2642 .enable_reg = 0x5024,
2643 .enable_mask = BIT(0),
2657 .halt_reg = 0x5028,
2659 .enable_reg = 0x5028,
2660 .enable_mask = BIT(0),
2674 .halt_reg = 0x506c,
2676 .enable_reg = 0x506c,
2677 .enable_mask = BIT(0),
2691 .halt_reg = 0x5064,
2693 .enable_reg = 0x5064,
2694 .enable_mask = BIT(0),
2708 .halt_reg = 0x405c,
2710 .enable_reg = 0x405c,
2711 .enable_mask = BIT(0),
2725 .halt_reg = 0x4058,
2727 .enable_reg = 0x4058,
2728 .enable_mask = BIT(0),
2742 .halt_reg = 0x402c,
2744 .enable_reg = 0x402c,
2745 .enable_mask = BIT(0),
2759 .halt_reg = 0x4028,
2761 .enable_reg = 0x4028,
2762 .enable_mask = BIT(0),
2776 .halt_reg = 0x40b0,
2778 .enable_reg = 0x40b0,
2779 .enable_mask = BIT(0),
2793 .halt_reg = 0x403c,
2795 .enable_reg = 0x403c,
2796 .enable_mask = BIT(0),
2810 .halt_reg = 0x1030,
2812 .enable_reg = 0x1030,
2813 .enable_mask = BIT(0),
2827 .halt_reg = 0x1034,
2829 .enable_reg = 0x1034,
2830 .enable_mask = BIT(0),
2844 .halt_reg = 0x1048,
2846 .enable_reg = 0x1048,
2847 .enable_mask = BIT(0),
2861 .halt_reg = 0x104c,
2863 .enable_reg = 0x104c,
2864 .enable_mask = BIT(0),
2878 .halt_reg = 0x1038,
2880 .enable_reg = 0x1038,
2881 .enable_mask = BIT(0),
2895 .halt_reg = 0x1028,
2897 .enable_reg = 0x1028,
2898 .enable_mask = BIT(0),
2912 .halt_reg = 0x1430,
2914 .enable_reg = 0x1430,
2915 .enable_mask = BIT(0),
2929 .halt_reg = 0x143c,
2931 .enable_reg = 0x143c,
2932 .enable_mask = BIT(0),
2946 .halt_reg = 0x1440,
2948 .enable_reg = 0x1440,
2949 .enable_mask = BIT(0),
2963 .halt_reg = 0x1434,
2965 .enable_reg = 0x1434,
2966 .enable_mask = BIT(0),
2978 .halt_reg = 0x142c,
2980 .enable_reg = 0x142c,
2981 .enable_mask = BIT(0),
2995 .halt_reg = 0x1438,
2997 .enable_reg = 0x1438,
2998 .enable_mask = BIT(0),
3012 .halt_reg = 0x1428,
3014 .enable_reg = 0x1428,
3015 .enable_mask = BIT(0),
3032 .vco_val = 0x0,
3033 .vco_mask = 0x3 << 20,
3034 .pre_div_val = 0x0,
3035 .pre_div_mask = 0x7 << 12,
3036 .post_div_val = 0x0,
3037 .post_div_mask = 0x3 << 8,
3039 .main_output_mask = BIT(0),
3046 .vco_val = 0x0,
3047 .vco_mask = 0x3 << 20,
3048 .pre_div_val = 0x0,
3049 .pre_div_mask = 0x7 << 12,
3050 .post_div_val = 0x0,
3051 .post_div_mask = 0x3 << 8,
3053 .main_output_mask = BIT(0),
3058 .gdscr = 0x1024,
3066 .gdscr = 0x1040,
3074 .gdscr = 0x1044,
3082 .gdscr = 0x2304,
3083 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
3092 .gdscr = 0x35a4,
3100 .gdscr = 0x36a4,
3101 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
3110 .gdscr = 0x4024,
3111 .cxcs = (unsigned int []){ 0x4028 },
3120 .gdscr = 0x4034,
3296 [MMSS_SPDM_RESET] = { 0x0200 },
3297 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3298 [VENUS0_RESET] = { 0x1020 },
3299 [VPU_RESET] = { 0x1400 },
3300 [MDSS_RESET] = { 0x2300 },
3301 [AVSYNC_RESET] = { 0x2400 },
3302 [CAMSS_PHY0_RESET] = { 0x3020 },
3303 [CAMSS_PHY1_RESET] = { 0x3050 },
3304 [CAMSS_PHY2_RESET] = { 0x3080 },
3305 [CAMSS_CSI0_RESET] = { 0x30b0 },
3306 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3307 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3308 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3309 [CAMSS_CSI1_RESET] = { 0x3120 },
3310 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3311 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3312 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3313 [CAMSS_CSI2_RESET] = { 0x3180 },
3314 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3315 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3316 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3317 [CAMSS_CSI3_RESET] = { 0x31e0 },
3318 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3319 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3320 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3321 [CAMSS_ISPIF_RESET] = { 0x3220 },
3322 [CAMSS_CCI_RESET] = { 0x3340 },
3323 [CAMSS_MCLK0_RESET] = { 0x3380 },
3324 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3325 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3326 [CAMSS_MCLK3_RESET] = { 0x3410 },
3327 [CAMSS_GP0_RESET] = { 0x3440 },
3328 [CAMSS_GP1_RESET] = { 0x3470 },
3329 [CAMSS_TOP_RESET] = { 0x3480 },
3330 [CAMSS_AHB_RESET] = { 0x3488 },
3331 [CAMSS_MICRO_RESET] = { 0x3490 },
3332 [CAMSS_JPEG_RESET] = { 0x35a0 },
3333 [CAMSS_VFE_RESET] = { 0x36a0 },
3334 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3335 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3336 [OXILI_RESET] = { 0x4020 },
3337 [OXILICX_RESET] = { 0x4030 },
3338 [OCMEMCX_RESET] = { 0x4050 },
3339 [MMSS_RBCRP_RESET] = { 0x4080 },
3340 [MMSSNOCAHB_RESET] = { 0x5020 },
3341 [MMSSNOCAXI_RESET] = { 0x5060 },
3359 .max_register = 0x5104,
3392 return 0; in mmcc_apq8084_probe()