Lines Matching +full:0 +full:x1020
40 .halt_reg = 0x1020,
42 .enable_reg = 0x1020,
43 .enable_mask = BIT(0),
58 { 1000000000, 2000000000, 0 },
64 .offset = 0x0,
79 .offset = 0x40,
94 { P_GPU_XO, 0 },
110 .cmd_rcgr = 0x1070,
111 .mnd_width = 0,
130 .halt_reg = 0x1098,
132 .hwcg_reg = 0x1098,
135 .enable_reg = 0x1098,
136 .enable_mask = BIT(0),
150 { P_GPU_XO, 0 },
162 F(19200000, P_GPU_XO, 1, 0, 0),
167 .cmd_rcgr = 0x10b0,
168 .mnd_width = 0,
181 F(19200000, P_GPU_XO, 1, 0, 0),
182 F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
187 .cmd_rcgr = 0x1030,
188 .mnd_width = 0,
201 .halt_reg = 0x10d0,
204 .enable_reg = 0x10d0,
205 .enable_mask = BIT(0),
219 .halt_reg = 0x1054,
222 .enable_reg = 0x1054,
223 .enable_mask = BIT(0),
237 .gdscr = 0x1004,
238 .gds_hw_ctrl = 0x1008,
247 .gdscr = 0x1094,
248 .clamp_io_ctrl = 0x130,
251 .cxcs = (unsigned int []){ 0x1098 },
267 [GPU_CX_BCR] = { 0x1000 },
268 [RBCPR_BCR] = { 0x1050 },
269 [GPU_GX_BCR] = { 0x1090 },
270 [SPDM_BCR] = { 0x10E0 },
289 .max_register = 0x9034,
314 .config_ctl_val = 0x4001055b, in gpucc_sdm660_probe()
315 .alpha = 0xaaaaab00, in gpucc_sdm660_probe()
317 .vco_val = 0x2 << 20, in gpucc_sdm660_probe()
318 .vco_mask = 0x3 << 20, in gpucc_sdm660_probe()
319 .main_output_mask = 0x1, in gpucc_sdm660_probe()
327 gpu_pll_config.l = 0x29; in gpucc_sdm660_probe()
328 gpu_pll_config.alpha_hi = 0xaa; in gpucc_sdm660_probe()
332 gpu_pll_config.l = 0x26; in gpucc_sdm660_probe()
333 gpu_pll_config.alpha_hi = 0x8a; in gpucc_sdm660_probe()