1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
16 #include <linux/reset-controller.h>
60 	if (sc->flags & POLL_CFG_GDSCR)  in gdsc_check_status()
61 		reg = sc->gdscr + CFG_GDSCR_OFFSET;  in gdsc_check_status()
62 	else if (sc->gds_hw_ctrl)  in gdsc_check_status()
63 		reg = sc->gds_hw_ctrl;  in gdsc_check_status()
65 		reg = sc->gdscr;  in gdsc_check_status()
67 	ret = regmap_read(sc->regmap, reg, &val);  in gdsc_check_status()
71 	if (sc->flags & POLL_CFG_GDSCR) {  in gdsc_check_status()
87 	return -EINVAL;  in gdsc_check_status()
94 	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);  in gdsc_hwctrl()
110 	return -ETIMEDOUT;  in gdsc_poll_status()
118 	if (status == GDSC_ON && sc->rsupply) {  in gdsc_toggle_logic()
119 		ret = regulator_enable(sc->rsupply);  in gdsc_toggle_logic()
124 	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);  in gdsc_toggle_logic()
129 	if ((sc->flags & VOTABLE) && status == GDSC_OFF) {  in gdsc_toggle_logic()
131 		 * Add a short delay here to ensure that an enable  in gdsc_toggle_logic()
139 	if (sc->gds_hw_ctrl) {  in gdsc_toggle_logic()
141 		 * The gds hw controller asserts/de-asserts the status bit soon  in gdsc_toggle_logic()
142 		 * after it receives a power on/off request from a master.  in gdsc_toggle_logic()
147 		 * Add a delay of 1 us between writing to the SW_COLLAPSE bit  in gdsc_toggle_logic()
154 	WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");  in gdsc_toggle_logic()
156 	if (!ret && status == GDSC_OFF && sc->rsupply) {  in gdsc_toggle_logic()
157 		ret = regulator_disable(sc->rsupply);  in gdsc_toggle_logic()
169 	for (i = 0; i < sc->reset_count; i++)  in gdsc_deassert_reset()
170 		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);  in gdsc_deassert_reset()
178 	for (i = 0; i < sc->reset_count; i++)  in gdsc_assert_reset()
179 		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);  in gdsc_assert_reset()
188 	if (!(sc->flags & NO_RET_PERIPH))  in gdsc_force_mem_on()
191 	for (i = 0; i < sc->cxc_count; i++)  in gdsc_force_mem_on()
192 		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);  in gdsc_force_mem_on()
200 	if (!(sc->flags & NO_RET_PERIPH))  in gdsc_clear_mem_on()
203 	for (i = 0; i < sc->cxc_count; i++)  in gdsc_clear_mem_on()
204 		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);  in gdsc_clear_mem_on()
209 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_deassert_clamp_io()
215 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_assert_clamp_io()
221 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_assert_reset_aon()
224 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,  in gdsc_assert_reset_aon()
232 	regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);  in gdsc_retain_ff_on()
240 	if (sc->pwrsts == PWRSTS_ON)  in gdsc_enable()
243 	if (sc->flags & SW_RESET) {  in gdsc_enable()
249 	if (sc->flags & CLAMP_IO) {  in gdsc_enable()
250 		if (sc->flags & AON_RESET)  in gdsc_enable()
259 	if (sc->pwrsts & PWRSTS_OFF)  in gdsc_enable()
263 	 * If clocks to this power domain were already on, they will take an  in gdsc_enable()
264 	 * additional 4 clock cycles to re-enable after the power domain is  in gdsc_enable()
265 	 * enabled. Delay to account for this. A delay is also needed to ensure  in gdsc_enable()
266 	 * clocks are not enabled within 400ns of enabling power to the  in gdsc_enable()
272 	if (sc->flags & HW_CTRL) {  in gdsc_enable()
277 		 * Wait for the GDSC to go through a power down and  in gdsc_enable()
280 		 * the GDSC can finish the power cycle.  in gdsc_enable()
281 		 * We wait 1us before returning to ensure the firmware  in gdsc_enable()
287 	if (sc->flags & RETAIN_FF_ENABLE)  in gdsc_enable()
298 	if (sc->pwrsts == PWRSTS_ON)  in gdsc_disable()
301 	/* Turn off HW trigger mode if supported */  in gdsc_disable()
302 	if (sc->flags & HW_CTRL) {  in gdsc_disable()
307 		 * Wait for the GDSC to go through a power down and  in gdsc_disable()
309 		 * bits for the gdsc before the power cycle is completed  in gdsc_disable()
319 	if (sc->pwrsts & PWRSTS_OFF)  in gdsc_disable()
326 	if (sc->flags & CLAMP_IO)  in gdsc_disable()
339 	 * Disable SW override: Use hardware state-machine for sequencing.  in gdsc_init()
345 	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);  in gdsc_init()
350 	if (sc->pwrsts == PWRSTS_ON) {  in gdsc_init()
362 		if (sc->rsupply) {  in gdsc_init()
363 			ret = regulator_enable(sc->rsupply);  in gdsc_init()
372 		if (sc->flags & VOTABLE) {  in gdsc_init()
373 			ret = regmap_update_bits(sc->regmap, sc->gdscr,  in gdsc_init()
380 		if (sc->flags & HW_CTRL) {  in gdsc_init()
388 		 * otherwise we end up turning off the GDSC and destroying all  in gdsc_init()
391 		if (sc->flags & RETAIN_FF_ENABLE)  in gdsc_init()
393 	} else if (sc->flags & ALWAYS_ON) {  in gdsc_init()
395 		gdsc_enable(&sc->pd);  in gdsc_init()
399 	if (on || (sc->pwrsts & PWRSTS_RET))  in gdsc_init()
404 	if (sc->flags & ALWAYS_ON)  in gdsc_init()
405 		sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;  in gdsc_init()
406 	if (!sc->pd.power_off)  in gdsc_init()
407 		sc->pd.power_off = gdsc_disable;  in gdsc_init()
408 	if (!sc->pd.power_on)  in gdsc_init()
409 		sc->pd.power_on = gdsc_enable;  in gdsc_init()
410 	pm_genpd_init(&sc->pd, NULL, !on);  in gdsc_init()
420 	struct device *dev = desc->dev;  in gdsc_register()
421 	struct gdsc **scs = desc->scs;  in gdsc_register()
422 	size_t num = desc->num;  in gdsc_register()
426 		return -ENOMEM;  in gdsc_register()
428 	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),  in gdsc_register()
430 	if (!data->domains)  in gdsc_register()
431 		return -ENOMEM;  in gdsc_register()
434 		if (!scs[i] || !scs[i]->supply)  in gdsc_register()
437 		scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);  in gdsc_register()
438 		if (IS_ERR(scs[i]->rsupply))  in gdsc_register()
439 			return PTR_ERR(scs[i]->rsupply);  in gdsc_register()
442 	data->num_domains = num;  in gdsc_register()
446 		scs[i]->regmap = regmap;  in gdsc_register()
447 		scs[i]->rcdev = rcdev;  in gdsc_register()
451 		data->domains[i] = &scs[i]->pd;  in gdsc_register()
458 		if (scs[i]->parent)  in gdsc_register()
459 			pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);  in gdsc_register()
462 	return of_genpd_add_provider_onecell(dev->of_node, data);  in gdsc_register()
468 	struct device *dev = desc->dev;  in gdsc_unregister()
469 	struct gdsc **scs = desc->scs;  in gdsc_unregister()
470 	size_t num = desc->num;  in gdsc_unregister()
476 		if (scs[i]->parent)  in gdsc_unregister()
477 			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);  in gdsc_unregister()
479 	of_genpd_del_provider(dev->of_node);  in gdsc_unregister()
492  * ensure that the GX is off during this super special case. We do this by
496  * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
497  * driver. During power up, nothing will happen from the CPU (and the GMU will
498  * power up normally but during power down this will ensure that the GX domain
499  * is *really* off - this gives us a semi standard way of doing what we need.