Lines Matching +full:0 +full:x6a000
43 .offset = 0x0,
46 .enable_reg = 0x52018,
47 .enable_mask = BIT(0),
60 { 0x1, 2 },
65 .offset = 0x0,
82 .offset = 0x76000,
85 .enable_reg = 0x52018,
100 .offset = 0x1c000,
103 .enable_reg = 0x52018,
118 { P_BI_TCXO, 0 },
132 { P_BI_TCXO, 0 },
148 { P_BI_TCXO, 0 },
160 { P_BI_TCXO, 0 },
170 { P_PCIE_0_PIPE_CLK, 0 },
180 { P_PCIE_1_PIPE_CLK, 0 },
190 { P_BI_TCXO, 0 },
208 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
218 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
228 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
238 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
248 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
258 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
268 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
280 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
292 .reg = 0x6b054,
293 .shift = 0,
307 .reg = 0x8d054,
308 .shift = 0,
322 .reg = 0x75058,
323 .shift = 0,
337 .reg = 0x750c8,
338 .shift = 0,
352 .reg = 0x75048,
353 .shift = 0,
367 .reg = 0x77058,
368 .shift = 0,
382 .reg = 0x770c8,
383 .shift = 0,
397 .reg = 0x77048,
398 .shift = 0,
412 .reg = 0xf060,
413 .shift = 0,
427 .reg = 0x10060,
428 .shift = 0,
442 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
443 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
444 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
449 .cmd_rcgr = 0x64004,
464 .cmd_rcgr = 0x65004,
479 .cmd_rcgr = 0x66004,
494 F(9600000, P_BI_TCXO, 2, 0, 0),
495 F(19200000, P_BI_TCXO, 1, 0, 0),
500 .cmd_rcgr = 0x6b058,
515 F(19200000, P_BI_TCXO, 1, 0, 0),
516 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
521 .cmd_rcgr = 0x6b03c,
522 .mnd_width = 0,
536 .cmd_rcgr = 0x8d058,
551 .cmd_rcgr = 0x8d03c,
552 .mnd_width = 0,
566 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
571 .cmd_rcgr = 0x33010,
572 .mnd_width = 0,
588 F(19200000, P_BI_TCXO, 1, 0, 0),
593 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
596 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
609 .cmd_rcgr = 0x17010,
626 .cmd_rcgr = 0x17140,
643 .cmd_rcgr = 0x17270,
660 .cmd_rcgr = 0x173a0,
677 .cmd_rcgr = 0x174d0,
694 .cmd_rcgr = 0x17600,
711 .cmd_rcgr = 0x17730,
728 .cmd_rcgr = 0x17860,
739 F(19200000, P_BI_TCXO, 1, 0, 0),
744 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
747 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
751 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
764 .cmd_rcgr = 0x18010,
781 .cmd_rcgr = 0x18140,
798 .cmd_rcgr = 0x18270,
815 .cmd_rcgr = 0x183a0,
832 .cmd_rcgr = 0x184d0,
849 .cmd_rcgr = 0x18600,
866 .cmd_rcgr = 0x1e010,
883 .cmd_rcgr = 0x1e140,
900 .cmd_rcgr = 0x1e270,
917 .cmd_rcgr = 0x1e3a0,
934 .cmd_rcgr = 0x1e4d0,
951 .cmd_rcgr = 0x1e600,
961 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
962 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
963 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
964 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
969 .cmd_rcgr = 0x1400c,
985 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
986 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
991 .cmd_rcgr = 0x1600c,
1006 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1007 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1008 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1009 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1014 .cmd_rcgr = 0x75024,
1029 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1030 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1031 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1036 .cmd_rcgr = 0x7506c,
1037 .mnd_width = 0,
1051 F(19200000, P_BI_TCXO, 1, 0, 0),
1056 .cmd_rcgr = 0x750a0,
1057 .mnd_width = 0,
1071 .cmd_rcgr = 0x75084,
1072 .mnd_width = 0,
1086 .cmd_rcgr = 0x77024,
1101 .cmd_rcgr = 0x7706c,
1102 .mnd_width = 0,
1116 .cmd_rcgr = 0x770a0,
1117 .mnd_width = 0,
1131 .cmd_rcgr = 0x77084,
1132 .mnd_width = 0,
1146 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1147 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1148 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1149 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1154 .cmd_rcgr = 0xf020,
1169 .cmd_rcgr = 0xf038,
1170 .mnd_width = 0,
1184 .cmd_rcgr = 0x10020,
1199 .cmd_rcgr = 0x10038,
1200 .mnd_width = 0,
1214 .cmd_rcgr = 0xf064,
1215 .mnd_width = 0,
1229 .cmd_rcgr = 0x10064,
1230 .mnd_width = 0,
1244 .reg = 0xf050,
1245 .shift = 0,
1259 .reg = 0x10050,
1260 .shift = 0,
1275 .halt_reg = 0x6b080,
1278 .enable_reg = 0x52000,
1289 .halt_reg = 0x8d084,
1292 .enable_reg = 0x52000,
1302 .halt_reg = 0x9000c,
1304 .hwcg_reg = 0x9000c,
1307 .enable_reg = 0x52000,
1317 .halt_reg = 0x750cc,
1319 .hwcg_reg = 0x750cc,
1322 .enable_reg = 0x750cc,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0x750cc,
1339 .hwcg_reg = 0x750cc,
1342 .enable_reg = 0x750cc,
1357 .halt_reg = 0x770cc,
1359 .hwcg_reg = 0x770cc,
1362 .enable_reg = 0x770cc,
1363 .enable_mask = BIT(0),
1377 .halt_reg = 0x770cc,
1379 .hwcg_reg = 0x770cc,
1382 .enable_reg = 0x770cc,
1397 .halt_reg = 0xf080,
1399 .hwcg_reg = 0xf080,
1402 .enable_reg = 0xf080,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0x10080,
1419 .hwcg_reg = 0x10080,
1422 .enable_reg = 0x10080,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x38004,
1439 .hwcg_reg = 0x38004,
1442 .enable_reg = 0x52000,
1453 .halt_reg = 0x26010,
1455 .hwcg_reg = 0x26010,
1458 .enable_reg = 0x26010,
1459 .enable_mask = BIT(0),
1469 .halt_reg = 0x26014,
1471 .hwcg_reg = 0x26014,
1474 .enable_reg = 0x26014,
1475 .enable_mask = BIT(0),
1484 .halt_reg = 0xf07c,
1486 .hwcg_reg = 0xf07c,
1489 .enable_reg = 0xf07c,
1490 .enable_mask = BIT(0),
1504 .halt_reg = 0x1007c,
1506 .hwcg_reg = 0x1007c,
1509 .enable_reg = 0x1007c,
1510 .enable_mask = BIT(0),
1525 .halt_reg = 0x71154,
1527 .hwcg_reg = 0x71154,
1530 .enable_reg = 0x71154,
1531 .enable_mask = BIT(0),
1541 .halt_reg = 0x8d080,
1543 .hwcg_reg = 0x8d080,
1546 .enable_reg = 0x52000,
1557 .halt_reg = 0x2700c,
1559 .hwcg_reg = 0x2700c,
1562 .enable_reg = 0x2700c,
1563 .enable_mask = BIT(0),
1573 .halt_reg = 0x27014,
1575 .hwcg_reg = 0x27014,
1578 .enable_reg = 0x27014,
1579 .enable_mask = BIT(0),
1588 .halt_reg = 0x64000,
1591 .enable_reg = 0x64000,
1592 .enable_mask = BIT(0),
1606 .halt_reg = 0x65000,
1609 .enable_reg = 0x65000,
1610 .enable_mask = BIT(0),
1624 .halt_reg = 0x66000,
1627 .enable_reg = 0x66000,
1628 .enable_mask = BIT(0),
1645 .enable_reg = 0x52000,
1663 .enable_reg = 0x52000,
1678 .halt_reg = 0x8c014,
1681 .enable_reg = 0x8c014,
1682 .enable_mask = BIT(0),
1691 .halt_reg = 0x7100c,
1693 .hwcg_reg = 0x7100c,
1696 .enable_reg = 0x7100c,
1697 .enable_mask = BIT(0),
1706 .halt_reg = 0x71018,
1709 .enable_reg = 0x71018,
1710 .enable_mask = BIT(0),
1719 .halt_reg = 0x6b038,
1722 .enable_reg = 0x52000,
1737 .halt_reg = 0x8d038,
1740 .enable_reg = 0x52000,
1755 .halt_reg = 0x6b028,
1758 .enable_reg = 0x52008,
1773 .halt_reg = 0x6b024,
1775 .hwcg_reg = 0x6b024,
1778 .enable_reg = 0x52008,
1788 .halt_reg = 0x8c004,
1791 .enable_reg = 0x8c004,
1792 .enable_mask = BIT(0),
1802 .halt_reg = 0x6b01c,
1804 .hwcg_reg = 0x6b01c,
1807 .enable_reg = 0x52008,
1818 .halt_reg = 0x6b030,
1821 .enable_reg = 0x52008,
1836 .halt_reg = 0x6b014,
1838 .hwcg_reg = 0x6b014,
1841 .enable_reg = 0x52008,
1842 .enable_mask = BIT(0),
1851 .halt_reg = 0x6b010,
1854 .enable_reg = 0x52008,
1864 .halt_reg = 0x8d028,
1867 .enable_reg = 0x52000,
1882 .halt_reg = 0x8d024,
1884 .hwcg_reg = 0x8d024,
1887 .enable_reg = 0x52000,
1897 .halt_reg = 0x8c008,
1900 .enable_reg = 0x8c008,
1901 .enable_mask = BIT(0),
1911 .halt_reg = 0x8d01c,
1913 .hwcg_reg = 0x8d01c,
1916 .enable_reg = 0x52000,
1927 .halt_reg = 0x8d030,
1930 .enable_reg = 0x52000,
1945 .halt_reg = 0x8d014,
1947 .hwcg_reg = 0x8d014,
1950 .enable_reg = 0x52000,
1960 .halt_reg = 0x8d010,
1963 .enable_reg = 0x52000,
1973 .halt_reg = 0x3300c,
1976 .enable_reg = 0x3300c,
1977 .enable_mask = BIT(0),
1991 .halt_reg = 0x33004,
1993 .hwcg_reg = 0x33004,
1996 .enable_reg = 0x33004,
1997 .enable_mask = BIT(0),
2006 .halt_reg = 0x33008,
2009 .enable_reg = 0x33008,
2010 .enable_mask = BIT(0),
2019 .halt_reg = 0x26008,
2021 .hwcg_reg = 0x26008,
2024 .enable_reg = 0x26008,
2025 .enable_mask = BIT(0),
2034 .halt_reg = 0x2600c,
2036 .hwcg_reg = 0x2600c,
2039 .enable_reg = 0x2600c,
2040 .enable_mask = BIT(0),
2049 .halt_reg = 0x27008,
2051 .hwcg_reg = 0x27008,
2054 .enable_reg = 0x27008,
2055 .enable_mask = BIT(0),
2064 .halt_reg = 0x28008,
2066 .hwcg_reg = 0x28008,
2069 .enable_reg = 0x28008,
2070 .enable_mask = BIT(0),
2079 .halt_reg = 0x2800c,
2081 .hwcg_reg = 0x2800c,
2084 .enable_reg = 0x2800c,
2085 .enable_mask = BIT(0),
2094 .halt_reg = 0x23008,
2097 .enable_reg = 0x52008,
2107 .halt_reg = 0x23000,
2110 .enable_reg = 0x52008,
2120 .halt_reg = 0x1700c,
2123 .enable_reg = 0x52008,
2138 .halt_reg = 0x1713c,
2141 .enable_reg = 0x52008,
2156 .halt_reg = 0x1726c,
2159 .enable_reg = 0x52008,
2174 .halt_reg = 0x1739c,
2177 .enable_reg = 0x52008,
2192 .halt_reg = 0x174cc,
2195 .enable_reg = 0x52008,
2210 .halt_reg = 0x175fc,
2213 .enable_reg = 0x52008,
2228 .halt_reg = 0x1772c,
2231 .enable_reg = 0x52008,
2246 .halt_reg = 0x1785c,
2249 .enable_reg = 0x52008,
2264 .halt_reg = 0x23140,
2267 .enable_reg = 0x52008,
2277 .halt_reg = 0x23138,
2280 .enable_reg = 0x52008,
2290 .halt_reg = 0x18004,
2292 .hwcg_reg = 0x18004,
2295 .enable_reg = 0x52008,
2305 .halt_reg = 0x18008,
2307 .hwcg_reg = 0x18008,
2310 .enable_reg = 0x52008,
2320 .halt_reg = 0x1800c,
2323 .enable_reg = 0x52008,
2338 .halt_reg = 0x1813c,
2341 .enable_reg = 0x52008,
2356 .halt_reg = 0x1826c,
2359 .enable_reg = 0x52008,
2374 .halt_reg = 0x1839c,
2377 .enable_reg = 0x52008,
2392 .halt_reg = 0x184cc,
2395 .enable_reg = 0x52008,
2410 .halt_reg = 0x185fc,
2413 .enable_reg = 0x52008,
2428 .halt_reg = 0x23278,
2431 .enable_reg = 0x52010,
2441 .halt_reg = 0x23270,
2444 .enable_reg = 0x52010,
2445 .enable_mask = BIT(0),
2454 .halt_reg = 0x1e00c,
2457 .enable_reg = 0x52010,
2472 .halt_reg = 0x1e13c,
2475 .enable_reg = 0x52010,
2490 .halt_reg = 0x1e26c,
2493 .enable_reg = 0x52010,
2508 .halt_reg = 0x1e39c,
2511 .enable_reg = 0x52010,
2526 .halt_reg = 0x1e4cc,
2529 .enable_reg = 0x52010,
2544 .halt_reg = 0x1e5fc,
2547 .enable_reg = 0x52010,
2562 .halt_reg = 0x17004,
2564 .hwcg_reg = 0x17004,
2567 .enable_reg = 0x52008,
2577 .halt_reg = 0x17008,
2579 .hwcg_reg = 0x17008,
2582 .enable_reg = 0x52008,
2592 .halt_reg = 0x1e004,
2594 .hwcg_reg = 0x1e004,
2597 .enable_reg = 0x52010,
2607 .halt_reg = 0x1e008,
2609 .hwcg_reg = 0x1e008,
2612 .enable_reg = 0x52010,
2622 .halt_reg = 0x14008,
2625 .enable_reg = 0x14008,
2626 .enable_mask = BIT(0),
2635 .halt_reg = 0x14004,
2638 .enable_reg = 0x14004,
2639 .enable_mask = BIT(0),
2653 .halt_reg = 0x16008,
2656 .enable_reg = 0x16008,
2657 .enable_mask = BIT(0),
2666 .halt_reg = 0x16004,
2669 .enable_reg = 0x16004,
2670 .enable_mask = BIT(0),
2684 .halt_reg = 0x9044,
2687 .enable_reg = 0x9044,
2688 .enable_mask = BIT(0),
2697 .halt_reg = 0x8c000,
2700 .enable_reg = 0x8c000,
2701 .enable_mask = BIT(0),
2710 .halt_reg = 0x75018,
2712 .hwcg_reg = 0x75018,
2715 .enable_reg = 0x75018,
2716 .enable_mask = BIT(0),
2725 .halt_reg = 0x75010,
2727 .hwcg_reg = 0x75010,
2730 .enable_reg = 0x75010,
2731 .enable_mask = BIT(0),
2745 .halt_reg = 0x75010,
2747 .hwcg_reg = 0x75010,
2750 .enable_reg = 0x75010,
2765 .halt_reg = 0x75064,
2767 .hwcg_reg = 0x75064,
2770 .enable_reg = 0x75064,
2771 .enable_mask = BIT(0),
2785 .halt_reg = 0x75064,
2787 .hwcg_reg = 0x75064,
2790 .enable_reg = 0x75064,
2805 .halt_reg = 0x7509c,
2807 .hwcg_reg = 0x7509c,
2810 .enable_reg = 0x7509c,
2811 .enable_mask = BIT(0),
2825 .halt_reg = 0x7509c,
2827 .hwcg_reg = 0x7509c,
2830 .enable_reg = 0x7509c,
2846 .halt_reg = 0x75020,
2849 .enable_reg = 0x75020,
2850 .enable_mask = BIT(0),
2865 .halt_reg = 0x750b8,
2868 .enable_reg = 0x750b8,
2869 .enable_mask = BIT(0),
2884 .halt_reg = 0x7501c,
2887 .enable_reg = 0x7501c,
2888 .enable_mask = BIT(0),
2902 .halt_reg = 0x7505c,
2904 .hwcg_reg = 0x7505c,
2907 .enable_reg = 0x7505c,
2908 .enable_mask = BIT(0),
2922 .halt_reg = 0x7505c,
2924 .hwcg_reg = 0x7505c,
2927 .enable_reg = 0x7505c,
2942 .halt_reg = 0x77018,
2944 .hwcg_reg = 0x77018,
2947 .enable_reg = 0x77018,
2948 .enable_mask = BIT(0),
2957 .halt_reg = 0x77010,
2959 .hwcg_reg = 0x77010,
2962 .enable_reg = 0x77010,
2963 .enable_mask = BIT(0),
2977 .halt_reg = 0x77010,
2979 .hwcg_reg = 0x77010,
2982 .enable_reg = 0x77010,
2997 .halt_reg = 0x77064,
2999 .hwcg_reg = 0x77064,
3002 .enable_reg = 0x77064,
3003 .enable_mask = BIT(0),
3017 .halt_reg = 0x77064,
3019 .hwcg_reg = 0x77064,
3022 .enable_reg = 0x77064,
3037 .halt_reg = 0x7709c,
3039 .hwcg_reg = 0x7709c,
3042 .enable_reg = 0x7709c,
3043 .enable_mask = BIT(0),
3057 .halt_reg = 0x7709c,
3059 .hwcg_reg = 0x7709c,
3062 .enable_reg = 0x7709c,
3078 .halt_reg = 0x77020,
3081 .enable_reg = 0x77020,
3082 .enable_mask = BIT(0),
3097 .halt_reg = 0x770b8,
3100 .enable_reg = 0x770b8,
3101 .enable_mask = BIT(0),
3116 .halt_reg = 0x7701c,
3119 .enable_reg = 0x7701c,
3120 .enable_mask = BIT(0),
3134 .halt_reg = 0x7705c,
3136 .hwcg_reg = 0x7705c,
3139 .enable_reg = 0x7705c,
3140 .enable_mask = BIT(0),
3154 .halt_reg = 0x7705c,
3156 .hwcg_reg = 0x7705c,
3159 .enable_reg = 0x7705c,
3174 .halt_reg = 0xf010,
3177 .enable_reg = 0xf010,
3178 .enable_mask = BIT(0),
3192 .halt_reg = 0xf010,
3195 .enable_reg = 0xf010,
3205 .halt_reg = 0xf01c,
3208 .enable_reg = 0xf01c,
3209 .enable_mask = BIT(0),
3223 .halt_reg = 0xf018,
3226 .enable_reg = 0xf018,
3227 .enable_mask = BIT(0),
3236 .halt_reg = 0x10010,
3239 .enable_reg = 0x10010,
3240 .enable_mask = BIT(0),
3254 .halt_reg = 0x10010,
3257 .enable_reg = 0x10010,
3267 .halt_reg = 0x1001c,
3270 .enable_reg = 0x1001c,
3271 .enable_mask = BIT(0),
3285 .halt_reg = 0x10018,
3288 .enable_reg = 0x10018,
3289 .enable_mask = BIT(0),
3298 .halt_reg = 0xf054,
3301 .enable_reg = 0xf054,
3302 .enable_mask = BIT(0),
3316 .halt_reg = 0xf058,
3319 .enable_reg = 0xf058,
3320 .enable_mask = BIT(0),
3335 .halt_reg = 0xf05c,
3337 .hwcg_reg = 0xf05c,
3340 .enable_reg = 0xf05c,
3341 .enable_mask = BIT(0),
3355 .halt_reg = 0x8c010,
3358 .enable_reg = 0x8c010,
3359 .enable_mask = BIT(0),
3368 .halt_reg = 0x10054,
3371 .enable_reg = 0x10054,
3372 .enable_mask = BIT(0),
3386 .halt_reg = 0x10058,
3389 .enable_reg = 0x10058,
3390 .enable_mask = BIT(0),
3405 .halt_reg = 0x1005c,
3408 .enable_reg = 0x1005c,
3409 .enable_mask = BIT(0),
3424 .halt_reg = 0x28010,
3426 .hwcg_reg = 0x28010,
3429 .enable_reg = 0x28010,
3430 .enable_mask = BIT(0),
3440 .halt_reg = 0x28018,
3442 .hwcg_reg = 0x28018,
3445 .enable_reg = 0x28018,
3446 .enable_mask = BIT(0),
3455 .gdscr = 0x6b004,
3463 .gdscr = 0x8d004,
3471 .gdscr = 0x75004,
3479 .gdscr = 0x77004,
3487 .gdscr = 0xf004,
3495 .gdscr = 0x10004,
3503 .gdscr = 0x7d050,
3512 .gdscr = 0x7d058,
3521 .gdscr = 0x7d054,
3530 .gdscr = 0x7d06c,
3746 [GCC_CAMERA_BCR] = { 0x26000 },
3747 [GCC_DISPLAY_BCR] = { 0x27000 },
3748 [GCC_GPU_BCR] = { 0x71000 },
3749 [GCC_MMSS_BCR] = { 0xb000 },
3750 [GCC_PCIE_0_BCR] = { 0x6b000 },
3751 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3752 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3753 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3754 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3755 [GCC_PCIE_1_BCR] = { 0x8d000 },
3756 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3757 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3758 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3759 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3760 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3761 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3762 [GCC_PDM_BCR] = { 0x33000 },
3763 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3764 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3765 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3766 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3767 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3768 [GCC_SDCC2_BCR] = { 0x14000 },
3769 [GCC_SDCC4_BCR] = { 0x16000 },
3770 [GCC_UFS_CARD_BCR] = { 0x75000 },
3771 [GCC_UFS_PHY_BCR] = { 0x77000 },
3772 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3773 [GCC_USB30_SEC_BCR] = { 0x10000 },
3774 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3775 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3776 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3777 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3778 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3779 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3780 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3781 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
3782 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
3783 [GCC_VIDEO_BCR] = { 0x28000 },
3813 .max_register = 0x9c100,
3849 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3850 regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); in gcc_sm8350_probe()
3851 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3852 regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); in gcc_sm8350_probe()
3853 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3854 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); in gcc_sm8350_probe()
3855 regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); in gcc_sm8350_probe()