Lines Matching +full:0 +full:x6a000
36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
127 { P_BI_TCXO, 0 },
141 { P_BI_TCXO, 0 },
151 { P_BI_TCXO, 0 },
159 { P_BI_TCXO, 0 },
175 { P_BI_TCXO, 0 },
189 F(19200000, P_BI_TCXO, 1, 0, 0),
194 .cmd_rcgr = 0x48010,
195 .mnd_width = 0,
209 F(19200000, P_BI_TCXO, 1, 0, 0),
210 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
211 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
212 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
213 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
218 .cmd_rcgr = 0x64004,
232 .cmd_rcgr = 0x65004,
246 .cmd_rcgr = 0x66004,
260 F(9600000, P_BI_TCXO, 2, 0, 0),
261 F(19200000, P_BI_TCXO, 1, 0, 0),
266 .cmd_rcgr = 0x6b038,
280 .cmd_rcgr = 0x8d038,
294 .cmd_rcgr = 0x6038,
308 F(19200000, P_BI_TCXO, 1, 0, 0),
309 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
314 .cmd_rcgr = 0x6f014,
315 .mnd_width = 0,
328 F(9600000, P_BI_TCXO, 2, 0, 0),
329 F(19200000, P_BI_TCXO, 1, 0, 0),
330 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
335 .cmd_rcgr = 0x33010,
336 .mnd_width = 0,
351 F(19200000, P_BI_TCXO, 1, 0, 0),
355 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
357 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
360 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
364 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
376 .cmd_rcgr = 0x17010,
392 .cmd_rcgr = 0x17140,
403 F(19200000, P_BI_TCXO, 1, 0, 0),
407 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
409 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
412 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
424 .cmd_rcgr = 0x17270,
440 .cmd_rcgr = 0x173a0,
456 .cmd_rcgr = 0x174d0,
472 .cmd_rcgr = 0x17600,
488 .cmd_rcgr = 0x17730,
504 .cmd_rcgr = 0x17860,
520 .cmd_rcgr = 0x18010,
536 .cmd_rcgr = 0x18140,
552 .cmd_rcgr = 0x18270,
568 .cmd_rcgr = 0x183a0,
584 .cmd_rcgr = 0x184d0,
600 .cmd_rcgr = 0x18600,
616 .cmd_rcgr = 0x1e010,
632 .cmd_rcgr = 0x1e140,
648 .cmd_rcgr = 0x1e270,
664 .cmd_rcgr = 0x1e3a0,
680 .cmd_rcgr = 0x1e4d0,
696 .cmd_rcgr = 0x1e600,
706 F(19200000, P_BI_TCXO, 1, 0, 0),
707 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
708 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
709 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
710 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
715 .cmd_rcgr = 0x1400c,
730 F(19200000, P_BI_TCXO, 1, 0, 0),
731 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
732 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
733 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
738 .cmd_rcgr = 0x1600c,
757 .cmd_rcgr = 0x36010,
771 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
772 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
773 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
774 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
779 .cmd_rcgr = 0x75024,
793 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
794 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
795 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
796 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
801 .cmd_rcgr = 0x7506c,
802 .mnd_width = 0,
815 F(19200000, P_BI_TCXO, 1, 0, 0),
820 .cmd_rcgr = 0x750a0,
821 .mnd_width = 0,
834 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
835 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
836 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
841 .cmd_rcgr = 0x75084,
842 .mnd_width = 0,
855 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
856 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
857 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
858 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
859 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
864 .cmd_rcgr = 0x77024,
878 .cmd_rcgr = 0x7706c,
879 .mnd_width = 0,
892 .cmd_rcgr = 0x770a0,
893 .mnd_width = 0,
906 .cmd_rcgr = 0x77084,
907 .mnd_width = 0,
920 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
921 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
922 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
923 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
924 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
929 .cmd_rcgr = 0xf020,
943 .cmd_rcgr = 0xf038,
944 .mnd_width = 0,
957 .cmd_rcgr = 0x10020,
971 .cmd_rcgr = 0x10038,
972 .mnd_width = 0,
985 .cmd_rcgr = 0xf064,
986 .mnd_width = 0,
999 .cmd_rcgr = 0x10064,
1000 .mnd_width = 0,
1013 .reg = 0x48028,
1014 .shift = 0,
1028 .reg = 0xf050,
1029 .shift = 0,
1043 .reg = 0x10050,
1044 .shift = 0,
1058 .halt_reg = 0x9000c,
1061 .enable_reg = 0x9000c,
1062 .enable_mask = BIT(0),
1071 .halt_reg = 0x750cc,
1073 .hwcg_reg = 0x750cc,
1076 .enable_reg = 0x750cc,
1077 .enable_mask = BIT(0),
1091 .halt_reg = 0x770cc,
1093 .hwcg_reg = 0x770cc,
1096 .enable_reg = 0x770cc,
1097 .enable_mask = BIT(0),
1111 .halt_reg = 0xf080,
1114 .enable_reg = 0xf080,
1115 .enable_mask = BIT(0),
1129 .halt_reg = 0x10080,
1132 .enable_reg = 0x10080,
1133 .enable_mask = BIT(0),
1147 .halt_reg = 0x38004,
1149 .hwcg_reg = 0x38004,
1152 .enable_reg = 0x52000,
1162 .halt_reg = 0xb02c,
1165 .enable_reg = 0xb02c,
1166 .enable_mask = BIT(0),
1175 .halt_reg = 0xb030,
1178 .enable_reg = 0xb030,
1179 .enable_mask = BIT(0),
1188 .halt_reg = 0xb040,
1191 .enable_reg = 0xb040,
1192 .enable_mask = BIT(0),
1201 .halt_reg = 0xf07c,
1204 .enable_reg = 0xf07c,
1205 .enable_mask = BIT(0),
1219 .halt_reg = 0x1007c,
1222 .enable_reg = 0x1007c,
1223 .enable_mask = BIT(0),
1237 .halt_reg = 0x48000,
1240 .enable_reg = 0x52000,
1255 .halt_reg = 0x48004,
1258 .enable_reg = 0x48004,
1259 .enable_mask = BIT(0),
1268 .halt_reg = 0x71154,
1271 .enable_reg = 0x71154,
1272 .enable_mask = BIT(0),
1281 .halt_reg = 0x8d058,
1284 .enable_reg = 0x8d058,
1285 .enable_mask = BIT(0),
1294 .halt_reg = 0xb034,
1297 .enable_reg = 0xb034,
1298 .enable_mask = BIT(0),
1307 .halt_reg = 0xb038,
1310 .enable_reg = 0xb038,
1311 .enable_mask = BIT(0),
1320 .halt_reg = 0xb044,
1323 .enable_reg = 0xb044,
1324 .enable_mask = BIT(0),
1333 .halt_reg = 0x64000,
1336 .enable_reg = 0x64000,
1337 .enable_mask = BIT(0),
1351 .halt_reg = 0x65000,
1354 .enable_reg = 0x65000,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x66000,
1372 .enable_reg = 0x66000,
1373 .enable_mask = BIT(0),
1389 .enable_reg = 0x52000,
1406 .enable_reg = 0x52000,
1421 .halt_reg = 0x8c014,
1424 .enable_reg = 0x8c014,
1425 .enable_mask = BIT(0),
1434 .halt_reg = 0x7100c,
1437 .enable_reg = 0x7100c,
1438 .enable_mask = BIT(0),
1447 .halt_reg = 0x71018,
1450 .enable_reg = 0x71018,
1451 .enable_mask = BIT(0),
1460 .halt_reg = 0x4d008,
1463 .enable_reg = 0x4d008,
1464 .enable_mask = BIT(0),
1473 .halt_reg = 0x73008,
1476 .enable_reg = 0x73008,
1477 .enable_mask = BIT(0),
1486 .halt_reg = 0x73004,
1489 .enable_reg = 0x73004,
1490 .enable_mask = BIT(0),
1499 .halt_reg = 0x4d004,
1501 .hwcg_reg = 0x4d004,
1504 .enable_reg = 0x4d004,
1505 .enable_mask = BIT(0),
1514 .halt_reg = 0x4d00c,
1517 .enable_reg = 0x4d00c,
1518 .enable_mask = BIT(0),
1529 .enable_reg = 0x52000,
1546 .enable_reg = 0x52000,
1561 .halt_reg = 0x6f02c,
1564 .enable_reg = 0x6f02c,
1565 .enable_mask = BIT(0),
1579 .halt_reg = 0x6f030,
1582 .enable_reg = 0x6f030,
1583 .enable_mask = BIT(0),
1597 .halt_reg = 0x6f034,
1600 .enable_reg = 0x6f034,
1601 .enable_mask = BIT(0),
1615 .halt_reg = 0x6b028,
1618 .enable_reg = 0x52008,
1633 .halt_reg = 0x6b024,
1635 .hwcg_reg = 0x6b024,
1638 .enable_reg = 0x52008,
1648 .halt_reg = 0x6b01c,
1651 .enable_reg = 0x52008,
1661 .halt_reg = 0x6b02c,
1664 .enable_reg = 0x52008,
1674 .halt_reg = 0x6b014,
1676 .hwcg_reg = 0x6b014,
1679 .enable_reg = 0x52008,
1680 .enable_mask = BIT(0),
1689 .halt_reg = 0x6b010,
1692 .enable_reg = 0x52008,
1702 .halt_reg = 0x8d028,
1705 .enable_reg = 0x52000,
1720 .halt_reg = 0x8d024,
1722 .hwcg_reg = 0x8d024,
1725 .enable_reg = 0x52000,
1735 .halt_reg = 0x8d01c,
1738 .enable_reg = 0x52000,
1748 .halt_reg = 0x8d02c,
1751 .enable_reg = 0x52000,
1761 .halt_reg = 0x8d014,
1763 .hwcg_reg = 0x8d014,
1766 .enable_reg = 0x52000,
1776 .halt_reg = 0x8d010,
1779 .enable_reg = 0x52000,
1789 .halt_reg = 0x6028,
1792 .enable_reg = 0x52010,
1807 .halt_reg = 0x6024,
1809 .hwcg_reg = 0x6024,
1812 .enable_reg = 0x52010,
1822 .halt_reg = 0x601c,
1825 .enable_reg = 0x52010,
1835 .halt_reg = 0x602c,
1838 .enable_reg = 0x52010,
1848 .halt_reg = 0x6014,
1850 .hwcg_reg = 0x6014,
1853 .enable_reg = 0x52010,
1863 .halt_reg = 0x6010,
1866 .enable_reg = 0x52010,
1876 .halt_reg = 0x8c00c,
1879 .enable_reg = 0x8c00c,
1880 .enable_mask = BIT(0),
1889 .halt_reg = 0x6f004,
1892 .enable_reg = 0x6f004,
1893 .enable_mask = BIT(0),
1907 .halt_reg = 0x8c004,
1910 .enable_reg = 0x8c004,
1911 .enable_mask = BIT(0),
1920 .halt_reg = 0x8c008,
1923 .enable_reg = 0x8c008,
1924 .enable_mask = BIT(0),
1933 .halt_reg = 0x3300c,
1936 .enable_reg = 0x3300c,
1937 .enable_mask = BIT(0),
1951 .halt_reg = 0x33004,
1953 .hwcg_reg = 0x33004,
1956 .enable_reg = 0x33004,
1957 .enable_mask = BIT(0),
1966 .halt_reg = 0x33008,
1969 .enable_reg = 0x33008,
1970 .enable_mask = BIT(0),
1979 .halt_reg = 0x34004,
1982 .enable_reg = 0x52000,
1992 .halt_reg = 0xb018,
1994 .hwcg_reg = 0xb018,
1997 .enable_reg = 0xb018,
1998 .enable_mask = BIT(0),
2007 .halt_reg = 0xb01c,
2009 .hwcg_reg = 0xb01c,
2012 .enable_reg = 0xb01c,
2013 .enable_mask = BIT(0),
2022 .halt_reg = 0xb020,
2024 .hwcg_reg = 0xb020,
2027 .enable_reg = 0xb020,
2028 .enable_mask = BIT(0),
2037 .halt_reg = 0xb010,
2039 .hwcg_reg = 0xb010,
2042 .enable_reg = 0xb010,
2043 .enable_mask = BIT(0),
2052 .halt_reg = 0xb014,
2054 .hwcg_reg = 0xb014,
2057 .enable_reg = 0xb014,
2058 .enable_mask = BIT(0),
2067 .halt_reg = 0x23008,
2070 .enable_reg = 0x52008,
2080 .halt_reg = 0x23000,
2083 .enable_reg = 0x52008,
2093 .halt_reg = 0x1700c,
2096 .enable_reg = 0x52008,
2111 .halt_reg = 0x1713c,
2114 .enable_reg = 0x52008,
2129 .halt_reg = 0x1726c,
2132 .enable_reg = 0x52008,
2147 .halt_reg = 0x1739c,
2150 .enable_reg = 0x52008,
2165 .halt_reg = 0x174cc,
2168 .enable_reg = 0x52008,
2183 .halt_reg = 0x175fc,
2186 .enable_reg = 0x52008,
2201 .halt_reg = 0x1772c,
2204 .enable_reg = 0x52008,
2219 .halt_reg = 0x1785c,
2222 .enable_reg = 0x52008,
2237 .halt_reg = 0x23140,
2240 .enable_reg = 0x52008,
2250 .halt_reg = 0x23138,
2253 .enable_reg = 0x52008,
2263 .halt_reg = 0x1800c,
2266 .enable_reg = 0x52008,
2281 .halt_reg = 0x1813c,
2284 .enable_reg = 0x52008,
2299 .halt_reg = 0x1826c,
2302 .enable_reg = 0x52008,
2317 .halt_reg = 0x1839c,
2320 .enable_reg = 0x52008,
2335 .halt_reg = 0x184cc,
2338 .enable_reg = 0x52008,
2353 .halt_reg = 0x185fc,
2356 .enable_reg = 0x52008,
2371 .halt_reg = 0x23278,
2374 .enable_reg = 0x52010,
2384 .halt_reg = 0x23270,
2387 .enable_reg = 0x52010,
2388 .enable_mask = BIT(0),
2397 .halt_reg = 0x1e00c,
2400 .enable_reg = 0x52010,
2415 .halt_reg = 0x1e13c,
2418 .enable_reg = 0x52010,
2433 .halt_reg = 0x1e26c,
2436 .enable_reg = 0x52010,
2451 .halt_reg = 0x1e39c,
2454 .enable_reg = 0x52010,
2469 .halt_reg = 0x1e4cc,
2472 .enable_reg = 0x52010,
2487 .halt_reg = 0x1e5fc,
2490 .enable_reg = 0x52010,
2505 .halt_reg = 0x17004,
2508 .enable_reg = 0x52008,
2518 .halt_reg = 0x17008,
2520 .hwcg_reg = 0x17008,
2523 .enable_reg = 0x52008,
2533 .halt_reg = 0x18004,
2536 .enable_reg = 0x52008,
2546 .halt_reg = 0x18008,
2548 .hwcg_reg = 0x18008,
2551 .enable_reg = 0x52008,
2561 .halt_reg = 0x1e004,
2564 .enable_reg = 0x52010,
2574 .halt_reg = 0x1e008,
2576 .hwcg_reg = 0x1e008,
2579 .enable_reg = 0x52010,
2589 .halt_reg = 0x14008,
2592 .enable_reg = 0x14008,
2593 .enable_mask = BIT(0),
2602 .halt_reg = 0x14004,
2605 .enable_reg = 0x14004,
2606 .enable_mask = BIT(0),
2620 .halt_reg = 0x16008,
2623 .enable_reg = 0x16008,
2624 .enable_mask = BIT(0),
2633 .halt_reg = 0x16004,
2636 .enable_reg = 0x16004,
2637 .enable_mask = BIT(0),
2651 .halt_reg = 0x36004,
2654 .enable_reg = 0x36004,
2655 .enable_mask = BIT(0),
2664 .halt_reg = 0x3600c,
2667 .enable_reg = 0x3600c,
2668 .enable_mask = BIT(0),
2677 .halt_reg = 0x36008,
2680 .enable_reg = 0x36008,
2681 .enable_mask = BIT(0),
2695 .halt_reg = 0x8c000,
2698 .enable_reg = 0x8c000,
2699 .enable_mask = BIT(0),
2708 .halt_reg = 0x75018,
2710 .hwcg_reg = 0x75018,
2713 .enable_reg = 0x75018,
2714 .enable_mask = BIT(0),
2723 .halt_reg = 0x75010,
2725 .hwcg_reg = 0x75010,
2728 .enable_reg = 0x75010,
2729 .enable_mask = BIT(0),
2743 .halt_reg = 0x75064,
2745 .hwcg_reg = 0x75064,
2748 .enable_reg = 0x75064,
2749 .enable_mask = BIT(0),
2763 .halt_reg = 0x7509c,
2765 .hwcg_reg = 0x7509c,
2768 .enable_reg = 0x7509c,
2769 .enable_mask = BIT(0),
2783 .halt_reg = 0x75020,
2786 .enable_reg = 0x75020,
2787 .enable_mask = BIT(0),
2796 .halt_reg = 0x750b8,
2799 .enable_reg = 0x750b8,
2800 .enable_mask = BIT(0),
2809 .halt_reg = 0x7501c,
2812 .enable_reg = 0x7501c,
2813 .enable_mask = BIT(0),
2822 .halt_reg = 0x7505c,
2824 .hwcg_reg = 0x7505c,
2827 .enable_reg = 0x7505c,
2828 .enable_mask = BIT(0),
2842 .halt_reg = 0x77018,
2844 .hwcg_reg = 0x77018,
2847 .enable_reg = 0x77018,
2848 .enable_mask = BIT(0),
2857 .halt_reg = 0x77010,
2859 .hwcg_reg = 0x77010,
2862 .enable_reg = 0x77010,
2863 .enable_mask = BIT(0),
2877 .halt_reg = 0x77064,
2879 .hwcg_reg = 0x77064,
2882 .enable_reg = 0x77064,
2883 .enable_mask = BIT(0),
2897 .halt_reg = 0x7709c,
2899 .hwcg_reg = 0x7709c,
2902 .enable_reg = 0x7709c,
2903 .enable_mask = BIT(0),
2917 .halt_reg = 0x77020,
2920 .enable_reg = 0x77020,
2921 .enable_mask = BIT(0),
2930 .halt_reg = 0x770b8,
2933 .enable_reg = 0x770b8,
2934 .enable_mask = BIT(0),
2943 .halt_reg = 0x7701c,
2946 .enable_reg = 0x7701c,
2947 .enable_mask = BIT(0),
2956 .halt_reg = 0x7705c,
2958 .hwcg_reg = 0x7705c,
2961 .enable_reg = 0x7705c,
2962 .enable_mask = BIT(0),
2976 .halt_reg = 0xf010,
2979 .enable_reg = 0xf010,
2980 .enable_mask = BIT(0),
2994 .halt_reg = 0xf01c,
2997 .enable_reg = 0xf01c,
2998 .enable_mask = BIT(0),
3013 .halt_reg = 0xf018,
3016 .enable_reg = 0xf018,
3017 .enable_mask = BIT(0),
3026 .halt_reg = 0x10010,
3029 .enable_reg = 0x10010,
3030 .enable_mask = BIT(0),
3044 .halt_reg = 0x1001c,
3047 .enable_reg = 0x1001c,
3048 .enable_mask = BIT(0),
3063 .halt_reg = 0x10018,
3066 .enable_reg = 0x10018,
3067 .enable_mask = BIT(0),
3076 .halt_reg = 0xf054,
3079 .enable_reg = 0xf054,
3080 .enable_mask = BIT(0),
3094 .halt_reg = 0xf058,
3097 .enable_reg = 0xf058,
3098 .enable_mask = BIT(0),
3112 .halt_reg = 0xf05c,
3115 .enable_reg = 0xf05c,
3116 .enable_mask = BIT(0),
3125 .halt_reg = 0x8c010,
3128 .enable_reg = 0x8c010,
3129 .enable_mask = BIT(0),
3138 .halt_reg = 0x10054,
3141 .enable_reg = 0x10054,
3142 .enable_mask = BIT(0),
3156 .halt_reg = 0x10058,
3159 .enable_reg = 0x10058,
3160 .enable_mask = BIT(0),
3174 .halt_reg = 0x1005c,
3177 .enable_reg = 0x1005c,
3178 .enable_mask = BIT(0),
3187 .halt_reg = 0xb024,
3190 .enable_reg = 0xb024,
3191 .enable_mask = BIT(0),
3200 .halt_reg = 0xb028,
3203 .enable_reg = 0xb028,
3204 .enable_mask = BIT(0),
3213 .halt_reg = 0xb03c,
3216 .enable_reg = 0xb03c,
3217 .enable_mask = BIT(0),
3226 .gdscr = 0x6b004,
3234 .gdscr = 0x8d004,
3242 .gdscr = 0x6004,
3250 .gdscr = 0x75004,
3258 .gdscr = 0x77004,
3266 .gdscr = 0xf004,
3274 .gdscr = 0x10004,
3282 .gdscr = 0x7d050,
3291 .gdscr = 0x7d058,
3300 .gdscr = 0x7d054,
3309 .gdscr = 0x7d06c,
3537 [GCC_GPU_BCR] = { 0x71000 },
3538 [GCC_MMSS_BCR] = { 0xb000 },
3539 [GCC_NPU_BWMON_BCR] = { 0x73000 },
3540 [GCC_NPU_BCR] = { 0x4d000 },
3541 [GCC_PCIE_0_BCR] = { 0x6b000 },
3542 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3543 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3544 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3545 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3546 [GCC_PCIE_1_BCR] = { 0x8d000 },
3547 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3548 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3549 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3550 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3551 [GCC_PCIE_2_BCR] = { 0x6000 },
3552 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
3553 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
3554 [GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
3555 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
3556 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3557 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3558 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3559 [GCC_PDM_BCR] = { 0x33000 },
3560 [GCC_PRNG_BCR] = { 0x34000 },
3561 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3562 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3563 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3564 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3565 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3566 [GCC_SDCC2_BCR] = { 0x14000 },
3567 [GCC_SDCC4_BCR] = { 0x16000 },
3568 [GCC_TSIF_BCR] = { 0x36000 },
3569 [GCC_UFS_CARD_BCR] = { 0x75000 },
3570 [GCC_UFS_PHY_BCR] = { 0x77000 },
3571 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3572 [GCC_USB30_SEC_BCR] = { 0x10000 },
3573 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3574 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3575 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3576 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3577 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3578 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3579 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3580 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 },
3581 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 },
3611 .max_register = 0x9c100,
3644 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sm8250_probe()
3645 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sm8250_probe()
3653 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); in gcc_sm8250_probe()
3654 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); in gcc_sm8250_probe()
3655 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); in gcc_sm8250_probe()
3656 regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); in gcc_sm8250_probe()
3657 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sm8250_probe()
3658 regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); in gcc_sm8250_probe()