Lines Matching +full:0 +full:x2d000
34 { 249600000, 2000000000, 0 },
38 .offset = 0x0,
43 .enable_reg = 0x6d000,
44 .enable_mask = BIT(0),
57 { 0x0, 1 },
58 { 0x1, 2 },
59 { 0x3, 4 },
60 { 0x7, 8 },
65 .offset = 0x0,
82 .offset = 0x76000,
87 .enable_reg = 0x6d000,
101 .offset = 0x76000,
118 .offset = 0x74000,
123 .enable_reg = 0x6d000,
137 { P_BI_TCXO, 0 },
158 { P_BI_TCXO, 0 },
176 { P_BI_TCXO, 0 },
192 { P_BI_TCXO, 0 },
204 { P_BI_TCXO, 0 },
220 F(9600000, P_BI_TCXO, 2, 0, 0),
221 F(19200000, P_BI_TCXO, 1, 0, 0),
222 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
227 .cmd_rcgr = 0x11024,
242 F(4800000, P_BI_TCXO, 4, 0, 0),
243 F(9600000, P_BI_TCXO, 2, 0, 0),
245 F(19200000, P_BI_TCXO, 1, 0, 0),
248 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
253 .cmd_rcgr = 0x1100c,
267 .cmd_rcgr = 0x13024,
281 .cmd_rcgr = 0x1300c,
295 .cmd_rcgr = 0x15024,
309 .cmd_rcgr = 0x1500c,
323 .cmd_rcgr = 0x17024,
337 .cmd_rcgr = 0x1700c,
353 F(9600000, P_BI_TCXO, 2, 0, 0),
356 F(19200000, P_BI_TCXO, 1, 0, 0),
369 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
371 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
375 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
376 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
381 .cmd_rcgr = 0x1200c,
395 .cmd_rcgr = 0x1400c,
409 .cmd_rcgr = 0x1600c,
423 .cmd_rcgr = 0x1800c,
437 F(19200000, P_BI_TCXO, 1, 0, 0),
438 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
439 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
440 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
445 .cmd_rcgr = 0x24010,
446 .mnd_width = 0,
459 F(19200000, P_BI_TCXO, 1, 0, 0),
464 .cmd_rcgr = 0x2402c,
465 .mnd_width = 0,
480 F(19200000, P_BI_TCXO, 1, 0, 0),
481 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
482 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
483 F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0),
488 .cmd_rcgr = 0x47020,
502 F(19200000, P_BI_TCXO, 1, 0, 0),
503 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
504 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
509 .cmd_rcgr = 0x47038,
510 .mnd_width = 0,
523 F(19200000, P_BI_TCXO, 1, 0, 0),
524 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
525 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
526 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
527 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
532 .cmd_rcgr = 0x2b004,
546 .cmd_rcgr = 0x2c004,
560 .cmd_rcgr = 0x2d004,
574 .cmd_rcgr = 0x37034,
588 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
593 .cmd_rcgr = 0x37050,
594 .mnd_width = 0,
607 F(9600000, P_BI_TCXO, 2, 0, 0),
608 F(19200000, P_BI_TCXO, 1, 0, 0),
609 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
614 .cmd_rcgr = 0x19010,
615 .mnd_width = 0,
628 .cmd_rcgr = 0xf00c,
642 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
647 .cmd_rcgr = 0xb024,
661 F(19200000, P_BI_TCXO, 1, 0, 0),
666 .cmd_rcgr = 0xb03c,
667 .mnd_width = 0,
681 F(19200000, P_BI_TCXO, 1, 0, 0),
686 .cmd_rcgr = 0xb064,
700 .halt_reg = 0x22004,
703 .enable_reg = 0x22004,
704 .enable_mask = BIT(0),
713 .halt_reg = 0x10004,
716 .enable_reg = 0x6d008,
726 .halt_reg = 0x11008,
729 .enable_reg = 0x11008,
730 .enable_mask = BIT(0),
743 .halt_reg = 0x11004,
746 .enable_reg = 0x11004,
747 .enable_mask = BIT(0),
760 .halt_reg = 0x13008,
763 .enable_reg = 0x13008,
764 .enable_mask = BIT(0),
777 .halt_reg = 0x13004,
780 .enable_reg = 0x13004,
781 .enable_mask = BIT(0),
794 .halt_reg = 0x15008,
797 .enable_reg = 0x15008,
798 .enable_mask = BIT(0),
811 .halt_reg = 0x15004,
814 .enable_reg = 0x15004,
815 .enable_mask = BIT(0),
828 .halt_reg = 0x17008,
831 .enable_reg = 0x17008,
832 .enable_mask = BIT(0),
845 .halt_reg = 0x17004,
848 .enable_reg = 0x17004,
849 .enable_mask = BIT(0),
862 .halt_reg = 0x12004,
865 .enable_reg = 0x12004,
866 .enable_mask = BIT(0),
879 .halt_reg = 0x14004,
882 .enable_reg = 0x14004,
883 .enable_mask = BIT(0),
896 .halt_reg = 0x16004,
899 .enable_reg = 0x16004,
900 .enable_mask = BIT(0),
913 .halt_reg = 0x18004,
916 .enable_reg = 0x18004,
917 .enable_mask = BIT(0),
930 .halt_reg = 0x1c004,
932 .hwcg_reg = 0x1c004,
935 .enable_reg = 0x6d008,
945 .halt_reg = 0x2100c,
947 .hwcg_reg = 0x2100c,
950 .enable_reg = 0x6d008,
960 .halt_reg = 0x21008,
963 .enable_reg = 0x6d008,
973 .halt_reg = 0x21004,
976 .enable_reg = 0x6d008,
986 .halt_reg = 0x24008,
989 .enable_reg = 0x24008,
990 .enable_mask = BIT(0),
1003 .halt_reg = 0x4701c,
1006 .enable_reg = 0x4701c,
1007 .enable_mask = BIT(0),
1016 .halt_reg = 0x47018,
1019 .enable_reg = 0x47018,
1020 .enable_mask = BIT(0),
1033 .halt_reg = 0x47010,
1036 .enable_reg = 0x47010,
1037 .enable_mask = BIT(0),
1050 .halt_reg = 0x47014,
1053 .enable_reg = 0x47014,
1054 .enable_mask = BIT(0),
1063 .halt_reg = 0x2b000,
1066 .enable_reg = 0x2b000,
1067 .enable_mask = BIT(0),
1080 .halt_reg = 0x2c000,
1083 .enable_reg = 0x2c000,
1084 .enable_mask = BIT(0),
1097 .halt_reg = 0x2d000,
1100 .enable_reg = 0x2d000,
1101 .enable_mask = BIT(0),
1114 .halt_reg = 0x88004,
1117 .enable_reg = 0x88004,
1118 .enable_mask = BIT(0),
1127 .halt_reg = 0x37024,
1130 .enable_reg = 0x6d010,
1140 .halt_reg = 0x3701c,
1143 .enable_reg = 0x6d010,
1153 .halt_reg = 0x37018,
1156 .enable_reg = 0x6d010,
1166 .halt_reg = 0x3702c,
1169 .enable_reg = 0x6d010,
1179 .halt_reg = 0x37020,
1182 .enable_reg = 0x6d010,
1196 .halt_reg = 0x37028,
1199 .enable_reg = 0x6d010,
1213 .halt_reg = 0x37014,
1215 .hwcg_reg = 0x37014,
1218 .enable_reg = 0x6d010,
1219 .enable_mask = BIT(0),
1228 .halt_reg = 0x37010,
1231 .enable_reg = 0x6d010,
1241 .halt_reg = 0x1900c,
1244 .enable_reg = 0x1900c,
1245 .enable_mask = BIT(0),
1258 .halt_reg = 0x19004,
1260 .hwcg_reg = 0x19004,
1263 .enable_reg = 0x19004,
1264 .enable_mask = BIT(0),
1273 .halt_reg = 0x19008,
1276 .enable_reg = 0x19008,
1277 .enable_mask = BIT(0),
1286 .halt_reg = 0xf008,
1289 .enable_reg = 0xf008,
1290 .enable_mask = BIT(0),
1299 .halt_reg = 0xf004,
1302 .enable_reg = 0xf004,
1303 .enable_mask = BIT(0),
1316 .halt_reg = 0xb010,
1319 .enable_reg = 0xb010,
1320 .enable_mask = BIT(0),
1333 .halt_reg = 0xb020,
1336 .enable_reg = 0xb020,
1337 .enable_mask = BIT(0),
1350 .halt_reg = 0xb014,
1353 .enable_reg = 0xb014,
1354 .enable_mask = BIT(0),
1363 .halt_reg = 0xb01c,
1366 .enable_reg = 0xb01c,
1367 .enable_mask = BIT(0),
1376 .halt_reg = 0xb018,
1379 .enable_reg = 0xb018,
1380 .enable_mask = BIT(0),
1389 .halt_reg = 0xb058,
1392 .enable_reg = 0xb058,
1393 .enable_mask = BIT(0),
1406 .halt_reg = 0xb05c,
1409 .enable_reg = 0xb05c,
1410 .enable_mask = BIT(0),
1419 .halt_reg = 0x88000,
1422 .enable_reg = 0x88000,
1423 .enable_mask = BIT(0),
1432 .halt_reg = 0xe004,
1434 .hwcg_reg = 0xe004,
1437 .enable_reg = 0xe004,
1438 .enable_mask = BIT(0),
1447 .halt_reg = 0x22008,
1450 .enable_reg = 0x22008,
1451 .enable_mask = BIT(0),
1460 .gdscr = 0x0b004,
1468 .gdscr = 0x37004,
1476 .gdscr = 0x47004,
1576 [GCC_EMAC_BCR] = { 0x47000 },
1577 [GCC_PCIE_BCR] = { 0x37000 },
1578 [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1579 [GCC_PCIE_PHY_BCR] = { 0x39000 },
1580 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1581 [GCC_QUSB2PHY_BCR] = { 0xd000 },
1582 [GCC_USB30_BCR] = { 0xb000 },
1583 [GCC_USB3_PHY_BCR] = { 0xc000 },
1584 [GCC_USB3PHY_PHY_BCR] = { 0xc004 },
1585 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
1598 .max_register = 0x9b040,
1631 regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); in gcc_sdx55_probe()
1632 regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); in gcc_sdx55_probe()
1633 regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); in gcc_sdx55_probe()