Lines Matching +full:0 +full:x6a000
38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x76000,
58 .enable_reg = 0x52000,
72 { 0x0, 1 },
73 { 0x1, 2 },
74 { 0x3, 4 },
75 { 0x7, 8 },
80 .offset = 0x0,
97 { P_BI_TCXO, 0 },
109 { P_BI_TCXO, 0 },
123 { P_BI_TCXO, 0 },
133 { P_BI_TCXO, 0 },
143 { P_BI_TCXO, 0 },
151 { P_BI_TCXO, 0 },
184 { P_BI_TCXO, 0 },
199 F(19200000, P_BI_TCXO, 1, 0, 0),
204 .cmd_rcgr = 0x48014,
205 .mnd_width = 0,
218 F(19200000, P_BI_TCXO, 1, 0, 0),
223 .cmd_rcgr = 0x4815c,
224 .mnd_width = 0,
237 F(19200000, P_BI_TCXO, 1, 0, 0),
238 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
239 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
240 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
241 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
246 .cmd_rcgr = 0x64004,
260 .cmd_rcgr = 0x65004,
274 .cmd_rcgr = 0x66004,
288 F(9600000, P_BI_TCXO, 2, 0, 0),
289 F(19200000, P_BI_TCXO, 1, 0, 0),
294 .cmd_rcgr = 0x6b028,
308 .cmd_rcgr = 0x8d028,
322 F(19200000, P_BI_TCXO, 1, 0, 0),
323 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
328 .cmd_rcgr = 0x6f014,
329 .mnd_width = 0,
342 F(19200000, P_BI_TCXO, 1, 0, 0),
343 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
344 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
345 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
350 .cmd_rcgr = 0x4b008,
351 .mnd_width = 0,
364 F(9600000, P_BI_TCXO, 2, 0, 0),
365 F(19200000, P_BI_TCXO, 1, 0, 0),
366 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
371 .cmd_rcgr = 0x33010,
372 .mnd_width = 0,
387 F(19200000, P_BI_TCXO, 1, 0, 0),
394 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
398 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
411 .cmd_rcgr = 0x17034,
427 .cmd_rcgr = 0x17164,
443 .cmd_rcgr = 0x17294,
459 .cmd_rcgr = 0x173c4,
475 .cmd_rcgr = 0x174f4,
491 .cmd_rcgr = 0x17624,
507 .cmd_rcgr = 0x17754,
523 .cmd_rcgr = 0x17884,
539 .cmd_rcgr = 0x18018,
555 .cmd_rcgr = 0x18148,
571 .cmd_rcgr = 0x18278,
587 .cmd_rcgr = 0x183a8,
603 .cmd_rcgr = 0x184d8,
619 .cmd_rcgr = 0x18608,
635 .cmd_rcgr = 0x18738,
651 .cmd_rcgr = 0x18868,
661 F(9600000, P_BI_TCXO, 2, 0, 0),
662 F(19200000, P_BI_TCXO, 1, 0, 0),
663 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
664 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
665 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
666 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
671 .cmd_rcgr = 0x1400c,
686 F(9600000, P_BI_TCXO, 2, 0, 0),
687 F(19200000, P_BI_TCXO, 1, 0, 0),
689 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
690 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
695 .cmd_rcgr = 0x1600c,
714 .cmd_rcgr = 0x36010,
728 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
729 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
730 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
731 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
732 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
737 .cmd_rcgr = 0x7501c,
751 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
752 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
753 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
754 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
759 .cmd_rcgr = 0x7505c,
760 .mnd_width = 0,
773 .cmd_rcgr = 0x75090,
774 .mnd_width = 0,
787 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
788 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
789 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
794 .cmd_rcgr = 0x75074,
795 .mnd_width = 0,
808 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
809 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
810 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
811 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
812 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
817 .cmd_rcgr = 0x7701c,
831 .cmd_rcgr = 0x7705c,
832 .mnd_width = 0,
845 .cmd_rcgr = 0x77090,
846 .mnd_width = 0,
859 .cmd_rcgr = 0x77074,
860 .mnd_width = 0,
873 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
874 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
875 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
876 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
877 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
882 .cmd_rcgr = 0xf018,
896 F(19200000, P_BI_TCXO, 1, 0, 0),
897 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
898 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
899 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
904 .cmd_rcgr = 0xf030,
905 .mnd_width = 0,
918 .cmd_rcgr = 0x10018,
932 .cmd_rcgr = 0x10030,
933 .mnd_width = 0,
946 .cmd_rcgr = 0xf05c,
947 .mnd_width = 0,
960 .cmd_rcgr = 0x1005c,
961 .mnd_width = 0,
974 .cmd_rcgr = 0x7a030,
975 .mnd_width = 0,
988 F(19200000, P_BI_TCXO, 1, 0, 0),
989 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
990 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
995 .cmd_rcgr = 0x7a018,
996 .mnd_width = 0,
1009 .halt_reg = 0x90014,
1012 .enable_reg = 0x90014,
1013 .enable_mask = BIT(0),
1022 .halt_reg = 0x82028,
1024 .hwcg_reg = 0x82028,
1027 .enable_reg = 0x82028,
1028 .enable_mask = BIT(0),
1042 .halt_reg = 0x82024,
1044 .hwcg_reg = 0x82024,
1047 .enable_reg = 0x82024,
1048 .enable_mask = BIT(0),
1062 .halt_reg = 0x8201c,
1065 .enable_reg = 0x8201c,
1066 .enable_mask = BIT(0),
1080 .halt_reg = 0x82020,
1083 .enable_reg = 0x82020,
1084 .enable_mask = BIT(0),
1098 .halt_reg = 0x7a050,
1101 .enable_reg = 0x7a050,
1102 .enable_mask = BIT(0),
1116 .halt_reg = 0x38004,
1118 .hwcg_reg = 0x38004,
1121 .enable_reg = 0x52004,
1131 .halt_reg = 0xb008,
1133 .hwcg_reg = 0xb008,
1136 .enable_reg = 0xb008,
1137 .enable_mask = BIT(0),
1147 .halt_reg = 0xb020,
1150 .enable_reg = 0xb020,
1151 .enable_mask = BIT(0),
1160 .halt_reg = 0xb02c,
1163 .enable_reg = 0xb02c,
1164 .enable_mask = BIT(0),
1174 .halt_reg = 0x4100c,
1176 .hwcg_reg = 0x4100c,
1179 .enable_reg = 0x52004,
1189 .halt_reg = 0x41008,
1192 .enable_reg = 0x52004,
1202 .halt_reg = 0x41004,
1205 .enable_reg = 0x52004,
1215 .halt_reg = 0x502c,
1218 .enable_reg = 0x502c,
1219 .enable_mask = BIT(0),
1233 .halt_reg = 0x5030,
1236 .enable_reg = 0x5030,
1237 .enable_mask = BIT(0),
1251 .halt_reg = 0x48000,
1254 .enable_reg = 0x52004,
1269 .halt_reg = 0x48008,
1272 .enable_reg = 0x48008,
1273 .enable_mask = BIT(0),
1287 .halt_reg = 0x44038,
1290 .enable_reg = 0x44038,
1291 .enable_mask = BIT(0),
1300 .halt_reg = 0xb00c,
1302 .hwcg_reg = 0xb00c,
1305 .enable_reg = 0xb00c,
1306 .enable_mask = BIT(0),
1316 .halt_reg = 0xb024,
1319 .enable_reg = 0xb024,
1320 .enable_mask = BIT(0),
1331 .enable_reg = 0x52004,
1347 .enable_reg = 0x52004,
1361 .halt_reg = 0xb030,
1364 .enable_reg = 0xb030,
1365 .enable_mask = BIT(0),
1375 .halt_reg = 0x64000,
1378 .enable_reg = 0x64000,
1379 .enable_mask = BIT(0),
1393 .halt_reg = 0x65000,
1396 .enable_reg = 0x65000,
1397 .enable_mask = BIT(0),
1411 .halt_reg = 0x66000,
1414 .enable_reg = 0x66000,
1415 .enable_mask = BIT(0),
1429 .halt_reg = 0x71004,
1431 .hwcg_reg = 0x71004,
1434 .enable_reg = 0x71004,
1435 .enable_mask = BIT(0),
1447 .enable_reg = 0x52004,
1463 .enable_reg = 0x52004,
1477 .halt_reg = 0x8c010,
1480 .enable_reg = 0x8c010,
1481 .enable_mask = BIT(0),
1490 .halt_reg = 0x7100c,
1493 .enable_reg = 0x7100c,
1494 .enable_mask = BIT(0),
1503 .halt_reg = 0x71018,
1506 .enable_reg = 0x71018,
1507 .enable_mask = BIT(0),
1516 .halt_reg = 0x7a04c,
1519 .enable_reg = 0x7a04c,
1520 .enable_mask = BIT(0),
1534 .halt_reg = 0x8a008,
1537 .enable_reg = 0x8a008,
1538 .enable_mask = BIT(0),
1547 .halt_reg = 0x8a000,
1549 .hwcg_reg = 0x8a000,
1552 .enable_reg = 0x8a000,
1553 .enable_mask = BIT(0),
1564 .enable_reg = 0x52004,
1574 .halt_reg = 0x8a004,
1576 .hwcg_reg = 0x8a004,
1579 .enable_reg = 0x8a004,
1580 .enable_mask = BIT(0),
1589 .halt_reg = 0x8a154,
1592 .enable_reg = 0x8a154,
1593 .enable_mask = BIT(0),
1602 .halt_reg = 0x8a150,
1605 .enable_reg = 0x8a150,
1606 .enable_mask = BIT(0),
1615 .halt_reg = 0x7a048,
1618 .enable_reg = 0x7a048,
1619 .enable_mask = BIT(0),
1633 .halt_reg = 0x6b01c,
1636 .enable_reg = 0x5200c,
1651 .halt_reg = 0x6b018,
1653 .hwcg_reg = 0x6b018,
1656 .enable_reg = 0x5200c,
1666 .halt_reg = 0x8c00c,
1669 .enable_reg = 0x8c00c,
1670 .enable_mask = BIT(0),
1679 .halt_reg = 0x6b014,
1682 .enable_reg = 0x5200c,
1694 .enable_reg = 0x5200c,
1709 .halt_reg = 0x6b010,
1711 .hwcg_reg = 0x6b010,
1714 .enable_reg = 0x5200c,
1715 .enable_mask = BIT(0),
1724 .halt_reg = 0x6b00c,
1727 .enable_reg = 0x5200c,
1737 .halt_reg = 0x8d01c,
1740 .enable_reg = 0x52004,
1755 .halt_reg = 0x8d018,
1757 .hwcg_reg = 0x8d018,
1760 .enable_reg = 0x52004,
1770 .halt_reg = 0x8c02c,
1773 .enable_reg = 0x8c02c,
1774 .enable_mask = BIT(0),
1783 .halt_reg = 0x8d014,
1786 .enable_reg = 0x52004,
1798 .enable_reg = 0x52004,
1812 .halt_reg = 0x8d010,
1814 .hwcg_reg = 0x8d010,
1817 .enable_reg = 0x52004,
1827 .halt_reg = 0x8d00c,
1830 .enable_reg = 0x52004,
1840 .halt_reg = 0x6f004,
1843 .enable_reg = 0x6f004,
1844 .enable_mask = BIT(0),
1858 .halt_reg = 0x6f02c,
1861 .enable_reg = 0x6f02c,
1862 .enable_mask = BIT(0),
1876 .halt_reg = 0x3300c,
1879 .enable_reg = 0x3300c,
1880 .enable_mask = BIT(0),
1894 .halt_reg = 0x33004,
1896 .hwcg_reg = 0x33004,
1899 .enable_reg = 0x33004,
1900 .enable_mask = BIT(0),
1909 .halt_reg = 0x33008,
1912 .enable_reg = 0x33008,
1913 .enable_mask = BIT(0),
1922 .halt_reg = 0x34004,
1924 .hwcg_reg = 0x34004,
1927 .enable_reg = 0x52004,
1937 .halt_reg = 0xb014,
1939 .hwcg_reg = 0xb014,
1942 .enable_reg = 0xb014,
1943 .enable_mask = BIT(0),
1952 .halt_reg = 0xb018,
1954 .hwcg_reg = 0xb018,
1957 .enable_reg = 0xb018,
1958 .enable_mask = BIT(0),
1967 .halt_reg = 0xb010,
1969 .hwcg_reg = 0xb010,
1972 .enable_reg = 0xb010,
1973 .enable_mask = BIT(0),
1982 .halt_reg = 0x4b000,
1985 .enable_reg = 0x4b000,
1986 .enable_mask = BIT(0),
1995 .halt_reg = 0x4b004,
1998 .enable_reg = 0x4b004,
1999 .enable_mask = BIT(0),
2013 .halt_reg = 0x17030,
2016 .enable_reg = 0x5200c,
2031 .halt_reg = 0x17160,
2034 .enable_reg = 0x5200c,
2049 .halt_reg = 0x17290,
2052 .enable_reg = 0x5200c,
2067 .halt_reg = 0x173c0,
2070 .enable_reg = 0x5200c,
2085 .halt_reg = 0x174f0,
2088 .enable_reg = 0x5200c,
2103 .halt_reg = 0x17620,
2106 .enable_reg = 0x5200c,
2121 .halt_reg = 0x17750,
2124 .enable_reg = 0x5200c,
2139 .halt_reg = 0x17880,
2142 .enable_reg = 0x5200c,
2157 .halt_reg = 0x18014,
2160 .enable_reg = 0x5200c,
2175 .halt_reg = 0x18144,
2178 .enable_reg = 0x5200c,
2193 .halt_reg = 0x18274,
2196 .enable_reg = 0x5200c,
2211 .halt_reg = 0x183a4,
2214 .enable_reg = 0x5200c,
2229 .halt_reg = 0x184d4,
2232 .enable_reg = 0x5200c,
2247 .halt_reg = 0x18604,
2250 .enable_reg = 0x5200c,
2265 .halt_reg = 0x18734,
2268 .enable_reg = 0x5200c,
2283 .halt_reg = 0x18864,
2286 .enable_reg = 0x5200c,
2301 .halt_reg = 0x17004,
2304 .enable_reg = 0x5200c,
2314 .halt_reg = 0x17008,
2316 .hwcg_reg = 0x17008,
2319 .enable_reg = 0x5200c,
2329 .halt_reg = 0x1800c,
2332 .enable_reg = 0x5200c,
2342 .halt_reg = 0x18010,
2344 .hwcg_reg = 0x18010,
2347 .enable_reg = 0x5200c,
2357 .halt_reg = 0x14008,
2360 .enable_reg = 0x14008,
2361 .enable_mask = BIT(0),
2370 .halt_reg = 0x14004,
2373 .enable_reg = 0x14004,
2374 .enable_mask = BIT(0),
2388 .halt_reg = 0x16008,
2391 .enable_reg = 0x16008,
2392 .enable_mask = BIT(0),
2401 .halt_reg = 0x16004,
2404 .enable_reg = 0x16004,
2405 .enable_mask = BIT(0),
2419 .halt_reg = 0x414c,
2422 .enable_reg = 0x52004,
2423 .enable_mask = BIT(0),
2437 .halt_reg = 0x36004,
2440 .enable_reg = 0x36004,
2441 .enable_mask = BIT(0),
2450 .halt_reg = 0x3600c,
2453 .enable_reg = 0x3600c,
2454 .enable_mask = BIT(0),
2463 .halt_reg = 0x36008,
2466 .enable_reg = 0x36008,
2467 .enable_mask = BIT(0),
2481 .halt_reg = 0x75010,
2483 .hwcg_reg = 0x75010,
2486 .enable_reg = 0x75010,
2487 .enable_mask = BIT(0),
2496 .halt_reg = 0x7500c,
2498 .hwcg_reg = 0x7500c,
2501 .enable_reg = 0x7500c,
2502 .enable_mask = BIT(0),
2516 .halt_reg = 0x8c004,
2519 .enable_reg = 0x8c004,
2520 .enable_mask = BIT(0),
2529 .halt_reg = 0x75058,
2531 .hwcg_reg = 0x75058,
2534 .enable_reg = 0x75058,
2535 .enable_mask = BIT(0),
2549 .halt_reg = 0x7508c,
2551 .hwcg_reg = 0x7508c,
2554 .enable_reg = 0x7508c,
2555 .enable_mask = BIT(0),
2571 .enable_reg = 0x75018,
2572 .enable_mask = BIT(0),
2583 .enable_reg = 0x750a8,
2584 .enable_mask = BIT(0),
2595 .enable_reg = 0x75014,
2596 .enable_mask = BIT(0),
2605 .halt_reg = 0x75054,
2607 .hwcg_reg = 0x75054,
2610 .enable_reg = 0x75054,
2611 .enable_mask = BIT(0),
2625 .halt_reg = 0x8c000,
2628 .enable_reg = 0x8c000,
2629 .enable_mask = BIT(0),
2638 .halt_reg = 0x77010,
2640 .hwcg_reg = 0x77010,
2643 .enable_reg = 0x77010,
2644 .enable_mask = BIT(0),
2653 .halt_reg = 0x7700c,
2655 .hwcg_reg = 0x7700c,
2658 .enable_reg = 0x7700c,
2659 .enable_mask = BIT(0),
2673 .halt_reg = 0x77058,
2675 .hwcg_reg = 0x77058,
2678 .enable_reg = 0x77058,
2679 .enable_mask = BIT(0),
2693 .halt_reg = 0x7708c,
2695 .hwcg_reg = 0x7708c,
2698 .enable_reg = 0x7708c,
2699 .enable_mask = BIT(0),
2715 .enable_reg = 0x77018,
2716 .enable_mask = BIT(0),
2727 .enable_reg = 0x770a8,
2728 .enable_mask = BIT(0),
2739 .enable_reg = 0x77014,
2740 .enable_mask = BIT(0),
2749 .halt_reg = 0x77054,
2751 .hwcg_reg = 0x77054,
2754 .enable_reg = 0x77054,
2755 .enable_mask = BIT(0),
2769 .halt_reg = 0xf00c,
2772 .enable_reg = 0xf00c,
2773 .enable_mask = BIT(0),
2787 .halt_reg = 0xf014,
2790 .enable_reg = 0xf014,
2791 .enable_mask = BIT(0),
2805 .halt_reg = 0xf010,
2808 .enable_reg = 0xf010,
2809 .enable_mask = BIT(0),
2818 .halt_reg = 0x1000c,
2821 .enable_reg = 0x1000c,
2822 .enable_mask = BIT(0),
2836 .halt_reg = 0x10014,
2839 .enable_reg = 0x10014,
2840 .enable_mask = BIT(0),
2854 .halt_reg = 0x10010,
2857 .enable_reg = 0x10010,
2858 .enable_mask = BIT(0),
2867 .halt_reg = 0x8c008,
2870 .enable_reg = 0x8c008,
2871 .enable_mask = BIT(0),
2880 .halt_reg = 0xf04c,
2883 .enable_reg = 0xf04c,
2884 .enable_mask = BIT(0),
2898 .halt_reg = 0xf050,
2901 .enable_reg = 0xf050,
2902 .enable_mask = BIT(0),
2918 .enable_reg = 0xf054,
2919 .enable_mask = BIT(0),
2928 .halt_reg = 0x8c028,
2931 .enable_reg = 0x8c028,
2932 .enable_mask = BIT(0),
2941 .halt_reg = 0x1004c,
2944 .enable_reg = 0x1004c,
2945 .enable_mask = BIT(0),
2959 .halt_reg = 0x10050,
2962 .enable_reg = 0x10050,
2963 .enable_mask = BIT(0),
2979 .enable_reg = 0x10054,
2980 .enable_mask = BIT(0),
2989 .halt_reg = 0x6a004,
2991 .hwcg_reg = 0x6a004,
2994 .enable_reg = 0x6a004,
2995 .enable_mask = BIT(0),
3004 .halt_reg = 0x7a00c,
3007 .enable_reg = 0x7a00c,
3008 .enable_mask = BIT(0),
3022 .halt_reg = 0x7a004,
3025 .enable_reg = 0x7a004,
3026 .enable_mask = BIT(0),
3040 .halt_reg = 0x7a008,
3043 .enable_reg = 0x7a008,
3044 .enable_mask = BIT(0),
3058 .halt_reg = 0xb004,
3060 .hwcg_reg = 0xb004,
3063 .enable_reg = 0xb004,
3064 .enable_mask = BIT(0),
3074 .halt_reg = 0xb01c,
3077 .enable_reg = 0xb01c,
3078 .enable_mask = BIT(0),
3087 .halt_reg = 0xb028,
3090 .enable_reg = 0xb028,
3091 .enable_mask = BIT(0),
3101 .halt_reg = 0x7a014,
3103 .hwcg_reg = 0x7a014,
3106 .enable_reg = 0x7a014,
3107 .enable_mask = BIT(0),
3116 .halt_reg = 0x7a010,
3119 .enable_reg = 0x7a010,
3120 .enable_mask = BIT(0),
3134 .halt_reg = 0x48190,
3137 .enable_reg = 0x48190,
3138 .enable_mask = BIT(0),
3148 .halt_reg = 0x48004,
3150 .hwcg_reg = 0x48004,
3153 .enable_reg = 0x52004,
3166 .halt_reg = 0x47000,
3169 .enable_reg = 0x47000,
3170 .enable_mask = BIT(0),
3180 .halt_reg = 0x47008,
3183 .enable_reg = 0x47008,
3184 .enable_mask = BIT(0),
3195 .gdscr = 0x6b004,
3204 .gdscr = 0x8d004,
3213 .gdscr = 0x75004,
3222 .gdscr = 0x77004,
3231 .gdscr = 0xf004,
3240 .gdscr = 0x10004,
3249 .gdscr = 0x7d030,
3258 .gdscr = 0x7d03c,
3267 .gdscr = 0x7d034,
3276 .gdscr = 0x7d038,
3285 .gdscr = 0x7d040,
3294 .gdscr = 0x7d048,
3303 .gdscr = 0x7d044,
3508 [GCC_MMSS_BCR] = { 0xb000 },
3509 [GCC_PCIE_0_BCR] = { 0x6b000 },
3510 [GCC_PCIE_1_BCR] = { 0x8d000 },
3511 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3512 [GCC_PDM_BCR] = { 0x33000 },
3513 [GCC_PRNG_BCR] = { 0x34000 },
3514 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3515 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3516 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3517 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3518 [GCC_SDCC2_BCR] = { 0x14000 },
3519 [GCC_SDCC4_BCR] = { 0x16000 },
3520 [GCC_TSIF_BCR] = { 0x36000 },
3521 [GCC_UFS_CARD_BCR] = { 0x75000 },
3522 [GCC_UFS_PHY_BCR] = { 0x77000 },
3523 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3524 [GCC_USB30_SEC_BCR] = { 0x10000 },
3525 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3526 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3527 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3528 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3529 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3530 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3531 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3532 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3533 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3562 .max_register = 0x182090,
3611 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sdm845_probe()
3612 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sdm845_probe()