Lines Matching +full:0 +full:x6a000
54 .offset = 0x0,
57 .enable_reg = 0x52000,
58 .enable_mask = BIT(0),
84 .offset = 0x00000,
97 .offset = 0x1000,
100 .enable_reg = 0x52000,
127 .offset = 0x1000,
140 .offset = 0x77000,
143 .enable_reg = 0x52000,
157 .offset = 0x77000,
171 { P_XO, 0 },
183 { P_XO, 0 },
193 { P_XO, 0 },
207 { P_XO, 0 },
217 { P_XO, 0 },
227 { P_XO, 0 },
245 { P_XO, 0 },
259 { P_XO, 0 },
273 F(19200000, P_XO, 1, 0, 0),
274 F(50000000, P_GPLL0, 12, 0, 0),
279 .cmd_rcgr = 0x19020,
280 .mnd_width = 0,
294 F(4800000, P_XO, 4, 0, 0),
295 F(9600000, P_XO, 2, 0, 0),
297 F(19200000, P_XO, 1, 0, 0),
299 F(50000000, P_GPLL0, 12, 0, 0),
304 .cmd_rcgr = 0x1900c,
318 .cmd_rcgr = 0x1b020,
319 .mnd_width = 0,
332 .cmd_rcgr = 0x1b00c,
346 .cmd_rcgr = 0x1d020,
347 .mnd_width = 0,
360 .cmd_rcgr = 0x1d00c,
374 .cmd_rcgr = 0x1f020,
375 .mnd_width = 0,
388 .cmd_rcgr = 0x1f00c,
406 F(19200000, P_XO, 1, 0, 0),
409 F(40000000, P_GPLL0, 15, 0, 0),
411 F(48000000, P_GPLL0, 12.5, 0, 0),
415 F(60000000, P_GPLL0, 10, 0, 0),
416 F(63157895, P_GPLL0, 9.5, 0, 0),
421 .cmd_rcgr = 0x1a00c,
435 .cmd_rcgr = 0x1c00c,
449 .cmd_rcgr = 0x26020,
450 .mnd_width = 0,
463 .cmd_rcgr = 0x2600c,
477 .cmd_rcgr = 0x28020,
478 .mnd_width = 0,
491 .cmd_rcgr = 0x2800c,
505 .cmd_rcgr = 0x2a020,
506 .mnd_width = 0,
519 .cmd_rcgr = 0x2a00c,
533 .cmd_rcgr = 0x2c020,
534 .mnd_width = 0,
547 .cmd_rcgr = 0x2c00c,
561 .cmd_rcgr = 0x2700c,
575 .cmd_rcgr = 0x2900c,
589 F(19200000, P_XO, 1, 0, 0),
590 F(100000000, P_GPLL0, 6, 0, 0),
591 F(200000000, P_GPLL0, 3, 0, 0),
596 .cmd_rcgr = 0x64004,
610 .cmd_rcgr = 0x65004,
624 .cmd_rcgr = 0x66004,
638 F(300000000, P_GPLL0, 2, 0, 0),
639 F(600000000, P_GPLL0, 1, 0, 0),
644 .cmd_rcgr = 0x4805c,
645 .mnd_width = 0,
658 F(384000000, P_GPLL4, 4, 0, 0),
659 F(768000000, P_GPLL4, 2, 0, 0),
660 F(1536000000, P_GPLL4, 1, 0, 0),
665 .cmd_rcgr = 0x48074,
666 .mnd_width = 0,
679 F(19200000, P_XO, 1, 0, 0),
684 .cmd_rcgr = 0x48044,
685 .mnd_width = 0,
698 F(60000000, P_GPLL0, 10, 0, 0),
703 .cmd_rcgr = 0x33010,
704 .mnd_width = 0,
717 F(19200000, P_XO, 1, 0, 0),
718 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
719 F(160400000, P_GPLL1, 5, 0, 0),
720 F(267333333, P_GPLL1, 3, 0, 0),
725 .cmd_rcgr = 0x4d00c,
726 .mnd_width = 0,
743 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
744 F(100000000, P_GPLL0, 6, 0, 0),
745 F(192000000, P_GPLL4, 8, 0, 0),
746 F(384000000, P_GPLL4, 4, 0, 0),
751 .cmd_rcgr = 0x1602c,
765 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
766 F(150000000, P_GPLL0, 4, 0, 0),
767 F(200000000, P_GPLL0, 3, 0, 0),
768 F(300000000, P_GPLL0, 2, 0, 0),
773 .cmd_rcgr = 0x16010,
774 .mnd_width = 0,
791 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
792 F(100000000, P_GPLL0, 6, 0, 0),
793 F(192000000, P_GPLL4, 8, 0, 0),
794 F(200000000, P_GPLL0, 3, 0, 0),
799 .cmd_rcgr = 0x14010,
813 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
814 F(100000000, P_GPLL0, 6, 0, 0),
815 F(150000000, P_GPLL0, 4, 0, 0),
816 F(200000000, P_GPLL0, 3, 0, 0),
817 F(240000000, P_GPLL0, 2.5, 0, 0),
822 .cmd_rcgr = 0x75018,
836 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
837 F(150000000, P_GPLL0, 4, 0, 0),
838 F(300000000, P_GPLL0, 2, 0, 0),
843 .cmd_rcgr = 0x76010,
844 .mnd_width = 0,
857 .cmd_rcgr = 0x76044,
858 .mnd_width = 0,
871 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
872 F(75000000, P_GPLL0, 8, 0, 0),
873 F(150000000, P_GPLL0, 4, 0, 0),
878 .cmd_rcgr = 0x76028,
879 .mnd_width = 0,
892 F(19200000, P_XO, 1, 0, 0),
893 F(60000000, P_GPLL0, 10, 0, 0),
894 F(120000000, P_GPLL0, 5, 0, 0),
899 .cmd_rcgr = 0x2f010,
913 F(19200000, P_XO, 1, 0, 0),
914 F(60000000, P_GPLL0, 10, 0, 0),
919 .cmd_rcgr = 0x2f024,
920 .mnd_width = 0,
933 F(19200000, P_XO, 1, 0, 0),
934 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
935 F(120000000, P_GPLL0, 5, 0, 0),
936 F(133333333, P_GPLL0, 4.5, 0, 0),
937 F(150000000, P_GPLL0, 4, 0, 0),
938 F(200000000, P_GPLL0, 3, 0, 0),
939 F(240000000, P_GPLL0, 2.5, 0, 0),
944 .cmd_rcgr = 0xf014,
958 F(19200000, P_XO, 1, 0, 0),
959 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
960 F(60000000, P_GPLL0, 10, 0, 0),
965 .cmd_rcgr = 0xf028,
966 .mnd_width = 0,
979 F(1200000, P_XO, 16, 0, 0),
980 F(19200000, P_XO, 1, 0, 0),
985 .cmd_rcgr = 0x5000c,
986 .mnd_width = 0,
999 .halt_reg = 0x75034,
1002 .enable_reg = 0x75034,
1003 .enable_mask = BIT(0),
1016 .halt_reg = 0xf03c,
1019 .enable_reg = 0xf03c,
1020 .enable_mask = BIT(0),
1033 .halt_reg = 0x7106c,
1036 .enable_reg = 0x7106c,
1037 .enable_mask = BIT(0),
1046 .halt_reg = 0x48004,
1049 .enable_reg = 0x52004,
1059 .halt_reg = 0x4401c,
1062 .enable_reg = 0x4401c,
1063 .enable_mask = BIT(0),
1072 .halt_reg = 0x17004,
1075 .enable_reg = 0x52004,
1085 .halt_reg = 0x19008,
1088 .enable_reg = 0x19008,
1089 .enable_mask = BIT(0),
1103 .halt_reg = 0x19004,
1106 .enable_reg = 0x19004,
1107 .enable_mask = BIT(0),
1121 .halt_reg = 0x1b008,
1124 .enable_reg = 0x1b008,
1125 .enable_mask = BIT(0),
1139 .halt_reg = 0x1b004,
1142 .enable_reg = 0x1b004,
1143 .enable_mask = BIT(0),
1157 .halt_reg = 0x1d008,
1160 .enable_reg = 0x1d008,
1161 .enable_mask = BIT(0),
1175 .halt_reg = 0x1d004,
1178 .enable_reg = 0x1d004,
1179 .enable_mask = BIT(0),
1193 .halt_reg = 0x1f008,
1196 .enable_reg = 0x1f008,
1197 .enable_mask = BIT(0),
1211 .halt_reg = 0x1f004,
1214 .enable_reg = 0x1f004,
1215 .enable_mask = BIT(0),
1229 .halt_reg = 0x1a004,
1232 .enable_reg = 0x1a004,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x1c004,
1250 .enable_reg = 0x1c004,
1251 .enable_mask = BIT(0),
1265 .halt_reg = 0x25004,
1268 .enable_reg = 0x52004,
1278 .halt_reg = 0x26008,
1281 .enable_reg = 0x26008,
1282 .enable_mask = BIT(0),
1296 .halt_reg = 0x26004,
1299 .enable_reg = 0x26004,
1300 .enable_mask = BIT(0),
1314 .halt_reg = 0x28008,
1317 .enable_reg = 0x28008,
1318 .enable_mask = BIT(0),
1332 .halt_reg = 0x28004,
1335 .enable_reg = 0x28004,
1336 .enable_mask = BIT(0),
1350 .halt_reg = 0x2a008,
1353 .enable_reg = 0x2a008,
1354 .enable_mask = BIT(0),
1368 .halt_reg = 0x2a004,
1371 .enable_reg = 0x2a004,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x2c008,
1389 .enable_reg = 0x2c008,
1390 .enable_mask = BIT(0),
1404 .halt_reg = 0x2c004,
1407 .enable_reg = 0x2c004,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0x27004,
1425 .enable_reg = 0x27004,
1426 .enable_mask = BIT(0),
1440 .halt_reg = 0x29004,
1443 .enable_reg = 0x29004,
1444 .enable_mask = BIT(0),
1458 .halt_reg = 0x38004,
1461 .enable_reg = 0x52004,
1471 .halt_reg = 0x5058,
1474 .enable_reg = 0x5058,
1475 .enable_mask = BIT(0),
1488 .halt_reg = 0x5018,
1491 .enable_reg = 0x5018,
1492 .enable_mask = BIT(0),
1505 .halt_reg = 0x84004,
1507 .enable_reg = 0x84004,
1508 .enable_mask = BIT(0),
1517 .halt_reg = 0x64000,
1520 .enable_reg = 0x64000,
1521 .enable_mask = BIT(0),
1535 .halt_reg = 0x65000,
1538 .enable_reg = 0x65000,
1539 .enable_mask = BIT(0),
1553 .halt_reg = 0x66000,
1556 .enable_reg = 0x66000,
1557 .enable_mask = BIT(0),
1571 .halt_reg = 0x71010,
1574 .enable_reg = 0x71010,
1575 .enable_mask = BIT(0),
1584 .halt_reg = 0x71004,
1587 .enable_reg = 0x71004,
1588 .enable_mask = BIT(0),
1598 .halt_reg = 0x5200c,
1601 .enable_reg = 0x5200c,
1615 .halt_reg = 0x5200c,
1618 .enable_reg = 0x5200c,
1632 .halt_reg = 0x4808c,
1635 .enable_reg = 0x4808c,
1636 .enable_mask = BIT(0),
1646 .halt_reg = 0x48008,
1649 .enable_reg = 0x48008,
1650 .enable_mask = BIT(0),
1664 .halt_reg = 0x5200c,
1667 .enable_reg = 0x5200c,
1681 .halt_reg = 0x5200c,
1684 .enable_reg = 0x5200c,
1685 .enable_mask = BIT(0),
1698 .halt_reg = 0x9004,
1701 .enable_reg = 0x9004,
1702 .enable_mask = BIT(0),
1717 .halt_reg = 0x9000,
1720 .enable_reg = 0x9000,
1721 .enable_mask = BIT(0),
1730 .halt_reg = 0x8a000,
1732 .enable_reg = 0x8a000,
1733 .enable_mask = BIT(0),
1742 .halt_reg = 0x8a004,
1744 .hwcg_reg = 0x8a004,
1747 .enable_reg = 0x8a004,
1748 .enable_mask = BIT(0),
1757 .halt_reg = 0x8a040,
1759 .enable_reg = 0x8a040,
1760 .enable_mask = BIT(0),
1769 .halt_reg = 0x8a03c,
1771 .enable_reg = 0x8a03c,
1772 .enable_mask = BIT(0),
1781 .halt_reg = 0x3300c,
1784 .enable_reg = 0x3300c,
1785 .enable_mask = BIT(0),
1799 .halt_reg = 0x33004,
1802 .enable_reg = 0x33004,
1803 .enable_mask = BIT(0),
1812 .halt_reg = 0x34004,
1815 .enable_reg = 0x52004,
1825 .halt_reg = 0x4d004,
1828 .enable_reg = 0x4d004,
1829 .enable_mask = BIT(0),
1838 .halt_reg = 0x4d008,
1841 .enable_reg = 0x4d008,
1842 .enable_mask = BIT(0),
1856 .halt_reg = 0x88018,
1859 .enable_reg = 0x88018,
1860 .enable_mask = BIT(0),
1869 .halt_reg = 0x88014,
1872 .enable_reg = 0x88014,
1873 .enable_mask = BIT(0),
1882 .halt_reg = 0x16008,
1885 .enable_reg = 0x16008,
1886 .enable_mask = BIT(0),
1895 .halt_reg = 0x16004,
1898 .enable_reg = 0x16004,
1899 .enable_mask = BIT(0),
1913 .halt_reg = 0x1600c,
1916 .enable_reg = 0x1600c,
1917 .enable_mask = BIT(0),
1931 .halt_reg = 0x14008,
1934 .enable_reg = 0x14008,
1935 .enable_mask = BIT(0),
1944 .halt_reg = 0x14004,
1947 .enable_reg = 0x14004,
1948 .enable_mask = BIT(0),
1962 .halt_reg = 0x7500c,
1965 .enable_reg = 0x7500c,
1966 .enable_mask = BIT(0),
1975 .halt_reg = 0x75008,
1978 .enable_reg = 0x75008,
1979 .enable_mask = BIT(0),
1993 .halt_reg = 0x88008,
1996 .enable_reg = 0x88008,
1997 .enable_mask = BIT(0),
2006 .halt_reg = 0x7600c,
2009 .enable_reg = 0x7600c,
2010 .enable_mask = BIT(0),
2024 .halt_reg = 0x76040,
2027 .enable_reg = 0x76040,
2028 .enable_mask = BIT(0),
2042 .halt_reg = 0x75014,
2045 .enable_reg = 0x75014,
2046 .enable_mask = BIT(0),
2055 .halt_reg = 0x7605c,
2058 .enable_reg = 0x7605c,
2059 .enable_mask = BIT(0),
2068 .halt_reg = 0x75010,
2071 .enable_reg = 0x75010,
2072 .enable_mask = BIT(0),
2081 .halt_reg = 0x76008,
2084 .enable_reg = 0x76008,
2085 .enable_mask = BIT(0),
2099 .halt_reg = 0x2f004,
2102 .enable_reg = 0x2f004,
2103 .enable_mask = BIT(0),
2117 .halt_reg = 0x2f00c,
2120 .enable_reg = 0x2f00c,
2121 .enable_mask = BIT(0),
2135 .halt_reg = 0x2f008,
2138 .enable_reg = 0x2f008,
2139 .enable_mask = BIT(0),
2148 .halt_reg = 0xf008,
2151 .enable_reg = 0xf008,
2152 .enable_mask = BIT(0),
2166 .halt_reg = 0xf010,
2169 .enable_reg = 0xf010,
2170 .enable_mask = BIT(0),
2184 .halt_reg = 0xf00c,
2187 .enable_reg = 0xf00c,
2188 .enable_mask = BIT(0),
2197 .halt_reg = 0x8800c,
2200 .enable_reg = 0x8800c,
2201 .enable_mask = BIT(0),
2210 .halt_reg = 0x50000,
2213 .enable_reg = 0x50000,
2214 .enable_mask = BIT(0),
2228 .halt_reg = 0x50004,
2231 .enable_reg = 0x50004,
2232 .enable_mask = BIT(0),
2241 .halt_reg = 0x6a004,
2244 .enable_reg = 0x6a004,
2245 .enable_mask = BIT(0),
2254 .gdscr = 0x75004,
2255 .gds_hw_ctrl = 0x0,
2264 .gdscr = 0xf004,
2265 .gds_hw_ctrl = 0x0,
2274 .gdscr = 0x6b004,
2275 .gds_hw_ctrl = 0x0,
2424 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2425 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2426 [GCC_UFS_BCR] = { 0x75000 },
2427 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2428 [GCC_USB3_PHY_BCR] = { 0x50020 },
2429 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2430 [GCC_USB_20_BCR] = { 0x2f000 },
2431 [GCC_USB_30_BCR] = { 0xf000 },
2432 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2433 [GCC_MSS_RESTART] = { 0x79000 },
2440 .max_register = 0x94000,
2476 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_sdm660_probe()