Lines Matching +full:0 +full:x6a000
44 { 249600000, 2000000000, 0 },
48 .offset = 0x0,
53 .enable_reg = 0x52000,
54 .enable_mask = BIT(0),
67 { 0x0, 1 },
68 { 0x1, 2 },
69 { 0x3, 4 },
70 { 0x7, 8 },
75 .offset = 0x0,
90 .offset = 0x1000,
95 .enable_reg = 0x52000,
109 .offset = 0x76000,
114 .enable_reg = 0x52000,
128 .offset = 0x1a000,
133 .enable_reg = 0x52000,
147 { P_BI_TCXO, 0 },
159 { P_BI_TCXO, 0 },
173 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
203 { P_BI_TCXO, 0 },
211 { P_BI_TCXO, 0 },
221 { P_BI_TCXO, 0 },
235 { P_BI_TCXO, 0 },
251 { P_BI_TCXO, 0 },
265 F(19200000, P_BI_TCXO, 1, 0, 0),
266 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
267 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
272 .cmd_rcgr = 0x48014,
273 .mnd_width = 0,
287 F(19200000, P_BI_TCXO, 1, 0, 0),
288 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
289 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
290 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
295 .cmd_rcgr = 0x6038,
296 .mnd_width = 0,
312 F(19200000, P_BI_TCXO, 1, 0, 0),
313 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
314 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
315 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
316 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
321 .cmd_rcgr = 0x601c,
336 F(19200000, P_BI_TCXO, 1, 0, 0),
337 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
338 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
339 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
340 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
345 .cmd_rcgr = 0x64004,
360 .cmd_rcgr = 0x65004,
375 .cmd_rcgr = 0x66004,
390 .cmd_rcgr = 0xbe004,
405 .cmd_rcgr = 0xbf004,
420 F(19200000, P_BI_TCXO, 1, 0, 0),
421 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
422 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
423 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
424 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
425 F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
426 F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
431 .cmd_rcgr = 0x4d014,
432 .mnd_width = 0,
446 F(9600000, P_BI_TCXO, 2, 0, 0),
447 F(19200000, P_BI_TCXO, 1, 0, 0),
452 .cmd_rcgr = 0x6b02c,
467 .cmd_rcgr = 0x8d02c,
482 .cmd_rcgr = 0x9d02c,
497 .cmd_rcgr = 0xa302c,
512 F(19200000, P_BI_TCXO, 1, 0, 0),
513 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
518 .cmd_rcgr = 0x6f014,
519 .mnd_width = 0,
533 F(9600000, P_BI_TCXO, 2, 0, 0),
534 F(19200000, P_BI_TCXO, 1, 0, 0),
535 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
540 .cmd_rcgr = 0x33010,
541 .mnd_width = 0,
555 F(19200000, P_BI_TCXO, 1, 0, 0),
556 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
557 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
558 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
563 .cmd_rcgr = 0x4a00c,
564 .mnd_width = 0,
578 .cmd_rcgr = 0x4b008,
579 .mnd_width = 0,
595 F(19200000, P_BI_TCXO, 1, 0, 0),
599 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
601 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
604 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
608 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
614 .cmd_rcgr = 0x17148,
629 .cmd_rcgr = 0x17278,
644 .cmd_rcgr = 0x173a8,
659 .cmd_rcgr = 0x174d8,
674 .cmd_rcgr = 0x17608,
689 .cmd_rcgr = 0x17738,
704 .cmd_rcgr = 0x17868,
719 .cmd_rcgr = 0x17998,
734 .cmd_rcgr = 0x18148,
749 .cmd_rcgr = 0x18278,
764 .cmd_rcgr = 0x183a8,
779 .cmd_rcgr = 0x184d8,
794 .cmd_rcgr = 0x18608,
809 .cmd_rcgr = 0x18738,
824 .cmd_rcgr = 0x1e148,
839 .cmd_rcgr = 0x1e278,
854 .cmd_rcgr = 0x1e3a8,
869 .cmd_rcgr = 0x1e4d8,
884 .cmd_rcgr = 0x1e608,
899 .cmd_rcgr = 0x1e738,
915 F(9600000, P_BI_TCXO, 2, 0, 0),
916 F(19200000, P_BI_TCXO, 1, 0, 0),
918 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
919 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
920 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
925 .cmd_rcgr = 0x1400c,
941 F(9600000, P_BI_TCXO, 2, 0, 0),
942 F(19200000, P_BI_TCXO, 1, 0, 0),
943 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
944 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
945 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
950 .cmd_rcgr = 0x1600c,
970 .cmd_rcgr = 0x36010,
985 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
986 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
987 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
988 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
993 .cmd_rcgr = 0xa2020,
1008 .cmd_rcgr = 0xa2060,
1009 .mnd_width = 0,
1023 F(19200000, P_BI_TCXO, 1, 0, 0),
1028 .cmd_rcgr = 0xa2094,
1029 .mnd_width = 0,
1043 .cmd_rcgr = 0xa2078,
1044 .mnd_width = 0,
1058 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1059 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1060 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1061 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1062 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1067 .cmd_rcgr = 0x75020,
1082 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1083 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1084 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1089 .cmd_rcgr = 0x75060,
1090 .mnd_width = 0,
1104 .cmd_rcgr = 0x75094,
1105 .mnd_width = 0,
1119 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1120 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1121 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1126 .cmd_rcgr = 0x75078,
1127 .mnd_width = 0,
1141 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1142 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1143 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1144 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1145 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1150 .cmd_rcgr = 0x77020,
1165 .cmd_rcgr = 0x77060,
1166 .mnd_width = 0,
1180 .cmd_rcgr = 0x77094,
1181 .mnd_width = 0,
1195 .cmd_rcgr = 0x77078,
1196 .mnd_width = 0,
1210 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1211 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1212 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1213 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1214 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1219 .cmd_rcgr = 0xa601c,
1234 F(19200000, P_BI_TCXO, 1, 0, 0),
1235 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1236 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1237 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1242 .cmd_rcgr = 0xa6034,
1243 .mnd_width = 0,
1257 .cmd_rcgr = 0xf01c,
1272 .cmd_rcgr = 0xf034,
1273 .mnd_width = 0,
1287 .cmd_rcgr = 0x1001c,
1302 .cmd_rcgr = 0x10034,
1303 .mnd_width = 0,
1317 .cmd_rcgr = 0xa6068,
1318 .mnd_width = 0,
1332 .cmd_rcgr = 0xf060,
1333 .mnd_width = 0,
1347 .cmd_rcgr = 0x10060,
1348 .mnd_width = 0,
1362 .halt_reg = 0x90018,
1365 .enable_reg = 0x90018,
1366 .enable_mask = BIT(0),
1375 .halt_reg = 0x750c0,
1377 .hwcg_reg = 0x750c0,
1380 .enable_reg = 0x750c0,
1381 .enable_mask = BIT(0),
1395 .halt_reg = 0x750c0,
1397 .hwcg_reg = 0x750c0,
1400 .enable_reg = 0x750c0,
1415 .halt_reg = 0x770c0,
1417 .hwcg_reg = 0x770c0,
1420 .enable_reg = 0x770c0,
1421 .enable_mask = BIT(0),
1435 .halt_reg = 0x770c0,
1437 .hwcg_reg = 0x770c0,
1440 .enable_reg = 0x770c0,
1455 .halt_reg = 0xa6084,
1458 .enable_reg = 0xa6084,
1459 .enable_mask = BIT(0),
1473 .halt_reg = 0xf07c,
1476 .enable_reg = 0xf07c,
1477 .enable_mask = BIT(0),
1491 .halt_reg = 0x1007c,
1494 .enable_reg = 0x1007c,
1495 .enable_mask = BIT(0),
1509 .halt_reg = 0x38004,
1511 .hwcg_reg = 0x38004,
1514 .enable_reg = 0x52004,
1524 .halt_reg = 0xb030,
1527 .enable_reg = 0xb030,
1528 .enable_mask = BIT(0),
1537 .halt_reg = 0xb034,
1540 .enable_reg = 0xb034,
1541 .enable_mask = BIT(0),
1550 .halt_reg = 0xa609c,
1553 .enable_reg = 0xa609c,
1554 .enable_mask = BIT(0),
1568 .halt_reg = 0xf078,
1571 .enable_reg = 0xf078,
1572 .enable_mask = BIT(0),
1586 .halt_reg = 0x10078,
1589 .enable_reg = 0x10078,
1590 .enable_mask = BIT(0),
1605 .halt_reg = 0x48000,
1608 .enable_reg = 0x52004,
1623 .halt_reg = 0x48008,
1626 .enable_reg = 0x48008,
1627 .enable_mask = BIT(0),
1636 .halt_reg = 0x71154,
1639 .enable_reg = 0x71154,
1640 .enable_mask = BIT(0),
1649 .halt_reg = 0xb038,
1652 .enable_reg = 0xb038,
1653 .enable_mask = BIT(0),
1662 .halt_reg = 0xb03c,
1665 .enable_reg = 0xb03c,
1666 .enable_mask = BIT(0),
1675 .halt_reg = 0x6010,
1678 .enable_reg = 0x6010,
1679 .enable_mask = BIT(0),
1688 .halt_reg = 0x6034,
1691 .enable_reg = 0x6034,
1692 .enable_mask = BIT(0),
1706 .halt_reg = 0x6018,
1709 .enable_reg = 0x6018,
1710 .enable_mask = BIT(0),
1724 .halt_reg = 0x6014,
1726 .hwcg_reg = 0x6014,
1729 .enable_reg = 0x6014,
1730 .enable_mask = BIT(0),
1739 .halt_reg = 0x64000,
1742 .enable_reg = 0x64000,
1743 .enable_mask = BIT(0),
1757 .halt_reg = 0x65000,
1760 .enable_reg = 0x65000,
1761 .enable_mask = BIT(0),
1775 .halt_reg = 0x66000,
1778 .enable_reg = 0x66000,
1779 .enable_mask = BIT(0),
1793 .halt_reg = 0xbe000,
1796 .enable_reg = 0xbe000,
1797 .enable_mask = BIT(0),
1811 .halt_reg = 0xbf000,
1814 .enable_reg = 0xbf000,
1815 .enable_mask = BIT(0),
1831 .enable_reg = 0x52004,
1846 .enable_reg = 0x52004,
1861 .halt_reg = 0x7100c,
1864 .enable_reg = 0x7100c,
1865 .enable_mask = BIT(0),
1874 .halt_reg = 0x71018,
1877 .enable_reg = 0x71018,
1878 .enable_mask = BIT(0),
1887 .halt_reg = 0x4d010,
1890 .enable_reg = 0x4d010,
1891 .enable_mask = BIT(0),
1900 .halt_reg = 0x4d008,
1903 .enable_reg = 0x4d008,
1904 .enable_mask = BIT(0),
1920 .enable_reg = 0x52004,
1935 .enable_reg = 0x52004,
1950 .halt_reg = 0x4d00c,
1953 .enable_reg = 0x4d00c,
1954 .enable_mask = BIT(0),
1963 .halt_reg = 0x6f02c,
1966 .enable_reg = 0x6f02c,
1967 .enable_mask = BIT(0),
1981 .halt_reg = 0x6f030,
1984 .enable_reg = 0x6f030,
1985 .enable_mask = BIT(0),
1999 .halt_reg = 0x6f034,
2002 .enable_reg = 0x6f034,
2003 .enable_mask = BIT(0),
2017 .halt_reg = 0x6f038,
2020 .enable_reg = 0x6f038,
2021 .enable_mask = BIT(0),
2035 .halt_reg = 0x6b020,
2038 .enable_reg = 0x5200c,
2053 .halt_reg = 0x6b01c,
2055 .hwcg_reg = 0x6b01c,
2058 .enable_reg = 0x5200c,
2068 .halt_reg = 0x8c00c,
2071 .enable_reg = 0x8c00c,
2072 .enable_mask = BIT(0),
2081 .halt_reg = 0x6b018,
2084 .enable_reg = 0x5200c,
2094 .halt_reg = 0x6b024,
2097 .enable_reg = 0x5200c,
2107 .halt_reg = 0x6b014,
2109 .hwcg_reg = 0x6b014,
2112 .enable_reg = 0x5200c,
2113 .enable_mask = BIT(0),
2122 .halt_reg = 0x6b010,
2125 .enable_reg = 0x5200c,
2135 .halt_reg = 0x8d020,
2138 .enable_reg = 0x52004,
2153 .halt_reg = 0x8d01c,
2155 .hwcg_reg = 0x8d01c,
2158 .enable_reg = 0x52004,
2168 .halt_reg = 0x8c02c,
2171 .enable_reg = 0x8c02c,
2172 .enable_mask = BIT(0),
2181 .halt_reg = 0x8d018,
2184 .enable_reg = 0x52004,
2194 .halt_reg = 0x8d024,
2197 .enable_reg = 0x52004,
2207 .halt_reg = 0x8d014,
2209 .hwcg_reg = 0x8d014,
2212 .enable_reg = 0x52004,
2222 .halt_reg = 0x8d010,
2225 .enable_reg = 0x52004,
2235 .halt_reg = 0x9d020,
2238 .enable_reg = 0x52014,
2253 .halt_reg = 0x9d01c,
2255 .hwcg_reg = 0x9d01c,
2258 .enable_reg = 0x52014,
2268 .halt_reg = 0x8c014,
2271 .enable_reg = 0x8c014,
2272 .enable_mask = BIT(0),
2281 .halt_reg = 0x9d018,
2284 .enable_reg = 0x52014,
2294 .halt_reg = 0x9d024,
2297 .enable_reg = 0x52014,
2307 .halt_reg = 0x9d014,
2309 .hwcg_reg = 0x9d014,
2312 .enable_reg = 0x52014,
2322 .halt_reg = 0x9d010,
2325 .enable_reg = 0x52014,
2335 .halt_reg = 0xa3020,
2338 .enable_reg = 0x52014,
2353 .halt_reg = 0xa301c,
2355 .hwcg_reg = 0xa301c,
2358 .enable_reg = 0x52014,
2368 .halt_reg = 0x8c018,
2371 .enable_reg = 0x8c018,
2372 .enable_mask = BIT(0),
2381 .halt_reg = 0xa3018,
2384 .enable_reg = 0x52014,
2394 .halt_reg = 0xa3024,
2397 .enable_reg = 0x52014,
2407 .halt_reg = 0xa3014,
2409 .hwcg_reg = 0xa3014,
2412 .enable_reg = 0x52014,
2422 .halt_reg = 0xa3010,
2425 .enable_reg = 0x52014,
2435 .halt_reg = 0x6f004,
2438 .enable_reg = 0x6f004,
2439 .enable_mask = BIT(0),
2453 .halt_reg = 0x3300c,
2456 .enable_reg = 0x3300c,
2457 .enable_mask = BIT(0),
2471 .halt_reg = 0x33004,
2473 .hwcg_reg = 0x33004,
2476 .enable_reg = 0x33004,
2477 .enable_mask = BIT(0),
2486 .halt_reg = 0x33008,
2489 .enable_reg = 0x33008,
2490 .enable_mask = BIT(0),
2499 .halt_reg = 0x34004,
2502 .enable_reg = 0x52004,
2512 .halt_reg = 0xb018,
2514 .hwcg_reg = 0xb018,
2517 .enable_reg = 0xb018,
2518 .enable_mask = BIT(0),
2527 .halt_reg = 0xb01c,
2529 .hwcg_reg = 0xb01c,
2532 .enable_reg = 0xb01c,
2533 .enable_mask = BIT(0),
2542 .halt_reg = 0xb020,
2544 .hwcg_reg = 0xb020,
2547 .enable_reg = 0xb020,
2548 .enable_mask = BIT(0),
2557 .halt_reg = 0xb010,
2559 .hwcg_reg = 0xb010,
2562 .enable_reg = 0xb010,
2563 .enable_mask = BIT(0),
2572 .halt_reg = 0xb014,
2574 .hwcg_reg = 0xb014,
2577 .enable_reg = 0xb014,
2578 .enable_mask = BIT(0),
2587 .halt_reg = 0x4a004,
2590 .enable_reg = 0x4a004,
2591 .enable_mask = BIT(0),
2600 .halt_reg = 0x4a008,
2603 .enable_reg = 0x4a008,
2604 .enable_mask = BIT(0),
2618 .halt_reg = 0x4b000,
2621 .enable_reg = 0x4b000,
2622 .enable_mask = BIT(0),
2631 .halt_reg = 0x4b004,
2634 .enable_reg = 0x4b004,
2635 .enable_mask = BIT(0),
2649 .halt_reg = 0x17144,
2652 .enable_reg = 0x5200c,
2667 .halt_reg = 0x17274,
2670 .enable_reg = 0x5200c,
2685 .halt_reg = 0x173a4,
2688 .enable_reg = 0x5200c,
2703 .halt_reg = 0x174d4,
2706 .enable_reg = 0x5200c,
2721 .halt_reg = 0x17604,
2724 .enable_reg = 0x5200c,
2739 .halt_reg = 0x17734,
2742 .enable_reg = 0x5200c,
2757 .halt_reg = 0x17864,
2760 .enable_reg = 0x5200c,
2775 .halt_reg = 0x17994,
2778 .enable_reg = 0x5200c,
2793 .halt_reg = 0x18144,
2796 .enable_reg = 0x5200c,
2811 .halt_reg = 0x18274,
2814 .enable_reg = 0x5200c,
2829 .halt_reg = 0x183a4,
2832 .enable_reg = 0x5200c,
2847 .halt_reg = 0x184d4,
2850 .enable_reg = 0x5200c,
2865 .halt_reg = 0x18604,
2868 .enable_reg = 0x5200c,
2883 .halt_reg = 0x18734,
2886 .enable_reg = 0x5200c,
2901 .halt_reg = 0x1e144,
2904 .enable_reg = 0x52014,
2919 .halt_reg = 0x1e274,
2922 .enable_reg = 0x52014,
2937 .halt_reg = 0x1e3a4,
2940 .enable_reg = 0x52014,
2955 .halt_reg = 0x1e4d4,
2958 .enable_reg = 0x52014,
2973 .halt_reg = 0x1e604,
2976 .enable_reg = 0x52014,
2991 .halt_reg = 0x1e734,
2994 .enable_reg = 0x52014,
3009 .halt_reg = 0x17004,
3012 .enable_reg = 0x5200c,
3022 .halt_reg = 0x17008,
3024 .hwcg_reg = 0x17008,
3027 .enable_reg = 0x5200c,
3037 .halt_reg = 0x18004,
3040 .enable_reg = 0x5200c,
3050 .halt_reg = 0x18008,
3052 .hwcg_reg = 0x18008,
3055 .enable_reg = 0x5200c,
3065 .halt_reg = 0x1e004,
3068 .enable_reg = 0x52014,
3078 .halt_reg = 0x1e008,
3080 .hwcg_reg = 0x1e008,
3083 .enable_reg = 0x52014,
3093 .halt_reg = 0x14008,
3096 .enable_reg = 0x14008,
3097 .enable_mask = BIT(0),
3106 .halt_reg = 0x14004,
3109 .enable_reg = 0x14004,
3110 .enable_mask = BIT(0),
3124 .halt_reg = 0x16008,
3127 .enable_reg = 0x16008,
3128 .enable_mask = BIT(0),
3137 .halt_reg = 0x16004,
3140 .enable_reg = 0x16004,
3141 .enable_mask = BIT(0),
3156 .halt_reg = 0x4819c,
3159 .enable_reg = 0x52004,
3160 .enable_mask = BIT(0),
3174 .halt_reg = 0x36004,
3177 .enable_reg = 0x36004,
3178 .enable_mask = BIT(0),
3187 .halt_reg = 0x3600c,
3190 .enable_reg = 0x3600c,
3191 .enable_mask = BIT(0),
3200 .halt_reg = 0x36008,
3203 .enable_reg = 0x36008,
3204 .enable_mask = BIT(0),
3218 .halt_reg = 0xa2014,
3220 .hwcg_reg = 0xa2014,
3223 .enable_reg = 0xa2014,
3224 .enable_mask = BIT(0),
3233 .halt_reg = 0xa2010,
3235 .hwcg_reg = 0xa2010,
3238 .enable_reg = 0xa2010,
3239 .enable_mask = BIT(0),
3253 .halt_reg = 0xa205c,
3255 .hwcg_reg = 0xa205c,
3258 .enable_reg = 0xa205c,
3259 .enable_mask = BIT(0),
3273 .halt_reg = 0xa2090,
3275 .hwcg_reg = 0xa2090,
3278 .enable_reg = 0xa2090,
3279 .enable_mask = BIT(0),
3293 .halt_reg = 0xa201c,
3296 .enable_reg = 0xa201c,
3297 .enable_mask = BIT(0),
3306 .halt_reg = 0xa20ac,
3309 .enable_reg = 0xa20ac,
3310 .enable_mask = BIT(0),
3319 .halt_reg = 0xa2018,
3322 .enable_reg = 0xa2018,
3323 .enable_mask = BIT(0),
3332 .halt_reg = 0xa2058,
3334 .hwcg_reg = 0xa2058,
3337 .enable_reg = 0xa2058,
3338 .enable_mask = BIT(0),
3352 .halt_reg = 0x75014,
3354 .hwcg_reg = 0x75014,
3357 .enable_reg = 0x75014,
3358 .enable_mask = BIT(0),
3367 .halt_reg = 0x75010,
3369 .hwcg_reg = 0x75010,
3372 .enable_reg = 0x75010,
3373 .enable_mask = BIT(0),
3387 .halt_reg = 0x75010,
3389 .hwcg_reg = 0x75010,
3392 .enable_reg = 0x75010,
3407 .halt_reg = 0x7505c,
3409 .hwcg_reg = 0x7505c,
3412 .enable_reg = 0x7505c,
3413 .enable_mask = BIT(0),
3427 .halt_reg = 0x7505c,
3429 .hwcg_reg = 0x7505c,
3432 .enable_reg = 0x7505c,
3447 .halt_reg = 0x75090,
3449 .hwcg_reg = 0x75090,
3452 .enable_reg = 0x75090,
3453 .enable_mask = BIT(0),
3467 .halt_reg = 0x75090,
3469 .hwcg_reg = 0x75090,
3472 .enable_reg = 0x75090,
3487 .halt_reg = 0x7501c,
3490 .enable_reg = 0x7501c,
3491 .enable_mask = BIT(0),
3500 .halt_reg = 0x750ac,
3503 .enable_reg = 0x750ac,
3504 .enable_mask = BIT(0),
3513 .halt_reg = 0x75018,
3516 .enable_reg = 0x75018,
3517 .enable_mask = BIT(0),
3526 .halt_reg = 0x75058,
3528 .hwcg_reg = 0x75058,
3531 .enable_reg = 0x75058,
3532 .enable_mask = BIT(0),
3546 .halt_reg = 0x75058,
3548 .hwcg_reg = 0x75058,
3551 .enable_reg = 0x75058,
3566 .halt_reg = 0x77014,
3568 .hwcg_reg = 0x77014,
3571 .enable_reg = 0x77014,
3572 .enable_mask = BIT(0),
3581 .halt_reg = 0x77010,
3583 .hwcg_reg = 0x77010,
3586 .enable_reg = 0x77010,
3587 .enable_mask = BIT(0),
3601 .halt_reg = 0x77010,
3603 .hwcg_reg = 0x77010,
3606 .enable_reg = 0x77010,
3621 .halt_reg = 0x7705c,
3623 .hwcg_reg = 0x7705c,
3626 .enable_reg = 0x7705c,
3627 .enable_mask = BIT(0),
3641 .halt_reg = 0x7705c,
3643 .hwcg_reg = 0x7705c,
3646 .enable_reg = 0x7705c,
3661 .halt_reg = 0x77090,
3663 .hwcg_reg = 0x77090,
3666 .enable_reg = 0x77090,
3667 .enable_mask = BIT(0),
3681 .halt_reg = 0x77090,
3683 .hwcg_reg = 0x77090,
3686 .enable_reg = 0x77090,
3701 .halt_reg = 0x7701c,
3704 .enable_reg = 0x7701c,
3705 .enable_mask = BIT(0),
3714 .halt_reg = 0x770ac,
3717 .enable_reg = 0x770ac,
3718 .enable_mask = BIT(0),
3727 .halt_reg = 0x77018,
3730 .enable_reg = 0x77018,
3731 .enable_mask = BIT(0),
3740 .halt_reg = 0x77058,
3742 .hwcg_reg = 0x77058,
3745 .enable_reg = 0x77058,
3746 .enable_mask = BIT(0),
3760 .halt_reg = 0x77058,
3762 .hwcg_reg = 0x77058,
3765 .enable_reg = 0x77058,
3780 .halt_reg = 0xa6010,
3783 .enable_reg = 0xa6010,
3784 .enable_mask = BIT(0),
3797 .halt_reg = 0xa6018,
3800 .enable_reg = 0xa6018,
3801 .enable_mask = BIT(0),
3815 .halt_reg = 0xa6014,
3818 .enable_reg = 0xa6014,
3819 .enable_mask = BIT(0),
3828 .halt_reg = 0xf010,
3831 .enable_reg = 0xf010,
3832 .enable_mask = BIT(0),
3845 .halt_reg = 0xf018,
3848 .enable_reg = 0xf018,
3849 .enable_mask = BIT(0),
3863 .halt_reg = 0xf014,
3866 .enable_reg = 0xf014,
3867 .enable_mask = BIT(0),
3876 .halt_reg = 0x10010,
3879 .enable_reg = 0x10010,
3880 .enable_mask = BIT(0),
3893 .halt_reg = 0x10018,
3896 .enable_reg = 0x10018,
3897 .enable_mask = BIT(0),
3911 .halt_reg = 0x10014,
3914 .enable_reg = 0x10014,
3915 .enable_mask = BIT(0),
3924 .halt_reg = 0xa6050,
3927 .enable_reg = 0xa6050,
3928 .enable_mask = BIT(0),
3942 .halt_reg = 0xa6054,
3945 .enable_reg = 0xa6054,
3946 .enable_mask = BIT(0),
3960 .halt_reg = 0xa6058,
3963 .enable_reg = 0xa6058,
3964 .enable_mask = BIT(0),
3973 .halt_reg = 0xa605c,
3976 .enable_reg = 0xa605c,
3977 .enable_mask = BIT(0),
3986 .halt_reg = 0x8c008,
3989 .enable_reg = 0x8c008,
3990 .enable_mask = BIT(0),
3999 .halt_reg = 0xf050,
4002 .enable_reg = 0xf050,
4003 .enable_mask = BIT(0),
4017 .halt_reg = 0xf054,
4020 .enable_reg = 0xf054,
4021 .enable_mask = BIT(0),
4035 .halt_reg = 0xf058,
4038 .enable_reg = 0xf058,
4039 .enable_mask = BIT(0),
4048 .halt_reg = 0x8c028,
4051 .enable_reg = 0x8c028,
4052 .enable_mask = BIT(0),
4061 .halt_reg = 0x10050,
4064 .enable_reg = 0x10050,
4065 .enable_mask = BIT(0),
4079 .halt_reg = 0x10054,
4082 .enable_reg = 0x10054,
4083 .enable_mask = BIT(0),
4097 .halt_reg = 0x10058,
4100 .enable_reg = 0x10058,
4101 .enable_mask = BIT(0),
4110 .halt_reg = 0xb024,
4113 .enable_reg = 0xb024,
4114 .enable_mask = BIT(0),
4123 .halt_reg = 0xb028,
4126 .enable_reg = 0xb028,
4127 .enable_mask = BIT(0),
4136 .halt_reg = 0xb02c,
4139 .enable_reg = 0xb02c,
4140 .enable_mask = BIT(0),
4149 .gdscr = 0x10004,
4158 .gdscr = 0x6004,
4167 .gdscr = 0xf004,
4176 .gdscr = 0x6b004,
4185 .gdscr = 0x75004,
4194 .gdscr = 0x77004,
4203 .gdscr = 0x8d004,
4212 .gdscr = 0x9d004,
4221 .gdscr = 0xa2004,
4230 .gdscr = 0xa3004,
4239 .gdscr = 0xa6004,
4490 [GCC_EMAC_BCR] = { 0x6000 },
4491 [GCC_GPU_BCR] = { 0x71000 },
4492 [GCC_MMSS_BCR] = { 0xb000 },
4493 [GCC_NPU_BCR] = { 0x4d000 },
4494 [GCC_PCIE_0_BCR] = { 0x6b000 },
4495 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
4496 [GCC_PCIE_1_BCR] = { 0x8d000 },
4497 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
4498 [GCC_PCIE_2_BCR] = { 0x9d000 },
4499 [GCC_PCIE_2_PHY_BCR] = { 0xa701c },
4500 [GCC_PCIE_3_BCR] = { 0xa3000 },
4501 [GCC_PCIE_3_PHY_BCR] = { 0xa801c },
4502 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
4503 [GCC_PDM_BCR] = { 0x33000 },
4504 [GCC_PRNG_BCR] = { 0x34000 },
4505 [GCC_QSPI_1_BCR] = { 0x4a000 },
4506 [GCC_QSPI_BCR] = { 0x24008 },
4507 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
4508 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
4509 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
4510 [GCC_QUSB2PHY_5_BCR] = { 0x12010 },
4511 [GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
4512 [GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
4513 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
4514 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
4515 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
4516 [GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
4517 [GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
4518 [GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
4519 [GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
4520 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
4521 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
4522 [GCC_SDCC2_BCR] = { 0x14000 },
4523 [GCC_SDCC4_BCR] = { 0x16000 },
4524 [GCC_TSIF_BCR] = { 0x36000 },
4525 [GCC_UFS_CARD_2_BCR] = { 0xa2000 },
4526 [GCC_UFS_CARD_BCR] = { 0x75000 },
4527 [GCC_UFS_PHY_BCR] = { 0x77000 },
4528 [GCC_USB30_MP_BCR] = { 0xa6000 },
4529 [GCC_USB30_PRIM_BCR] = { 0xf000 },
4530 [GCC_USB30_SEC_BCR] = { 0x10000 },
4531 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
4532 [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
4533 [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
4534 [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
4555 .max_register = 0xc0004,
4590 regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4591 regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4592 regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4593 regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4594 regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4595 regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4596 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4597 regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4598 regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4599 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc8180x_probe()
4602 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc8180x_probe()
4603 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc8180x_probe()