Lines Matching +full:0 +full:x6a000
43 .offset = 0x0,
46 .enable_reg = 0x52010,
47 .enable_mask = BIT(0),
60 { 0x1, 2 },
65 .offset = 0x0,
82 { 0x3, 3 },
87 .offset = 0x0,
104 .offset = 0x1000,
107 .enable_reg = 0x52010,
121 .offset = 0x1e000,
124 .enable_reg = 0x52010,
138 .offset = 0x76000,
141 .enable_reg = 0x52010,
155 .offset = 0x1c000,
158 .enable_reg = 0x52010,
174 .enable_reg = 0x52000,
189 { P_BI_TCXO, 0 },
207 { P_BI_TCXO, 0 },
221 { P_BI_TCXO, 0 },
231 { P_BI_TCXO, 0 },
239 { P_BI_TCXO, 0 },
255 { P_BI_TCXO, 0 },
265 { P_PCIE_0_PIPE_CLK, 0 },
275 { P_PCIE_1_PIPE_CLK, 0 },
285 { P_BI_TCXO, 0 },
301 { P_BI_TCXO, 0 },
319 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
329 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
339 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
349 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
359 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
369 { P_BI_TCXO, 0 },
379 .reg = 0x6b054,
380 .shift = 0,
394 .reg = 0x8d054,
395 .shift = 0,
409 .reg = 0x77058,
410 .shift = 0,
424 .reg = 0x770c8,
425 .shift = 0,
439 .reg = 0x77048,
440 .shift = 0,
454 .reg = 0xf060,
455 .shift = 0,
469 .reg = 0x9e060,
470 .shift = 0,
483 F(19200000, P_BI_TCXO, 1, 0, 0),
488 .cmd_rcgr = 0x4800c,
489 .mnd_width = 0,
502 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
503 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
504 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
509 .cmd_rcgr = 0x64004,
523 .cmd_rcgr = 0x65004,
537 .cmd_rcgr = 0x66004,
551 F(9600000, P_BI_TCXO, 2, 0, 0),
552 F(19200000, P_BI_TCXO, 1, 0, 0),
557 .cmd_rcgr = 0x6b058,
571 F(19200000, P_BI_TCXO, 1, 0, 0),
572 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
577 .cmd_rcgr = 0x6b03c,
578 .mnd_width = 0,
591 .cmd_rcgr = 0x8d058,
605 .cmd_rcgr = 0x8d03c,
606 .mnd_width = 0,
620 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
625 .cmd_rcgr = 0x33010,
626 .mnd_width = 0,
640 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
641 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
642 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
643 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
648 .cmd_rcgr = 0x4b00c,
649 .mnd_width = 0,
664 F(19200000, P_BI_TCXO, 1, 0, 0),
669 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
672 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
676 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
688 .cmd_rcgr = 0x17010,
704 .cmd_rcgr = 0x17140,
715 F(19200000, P_BI_TCXO, 1, 0, 0),
721 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
724 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
736 .cmd_rcgr = 0x17270,
752 .cmd_rcgr = 0x173a0,
768 .cmd_rcgr = 0x174d0,
784 .cmd_rcgr = 0x17600,
800 .cmd_rcgr = 0x17730,
816 .cmd_rcgr = 0x17860,
832 .cmd_rcgr = 0x18010,
848 .cmd_rcgr = 0x18140,
864 .cmd_rcgr = 0x18270,
880 .cmd_rcgr = 0x183a0,
896 .cmd_rcgr = 0x184d0,
912 .cmd_rcgr = 0x18600,
928 .cmd_rcgr = 0x18730,
944 .cmd_rcgr = 0x18860,
955 F(19200000, P_BI_TCXO, 1, 0, 0),
957 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
958 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
959 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
960 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
961 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
966 .cmd_rcgr = 0x7500c,
980 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
981 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
982 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
987 .cmd_rcgr = 0x7502c,
988 .mnd_width = 0,
1002 F(19200000, P_BI_TCXO, 1, 0, 0),
1003 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1004 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1005 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1006 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1011 .cmd_rcgr = 0x1400c,
1027 F(19200000, P_BI_TCXO, 1, 0, 0),
1028 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1029 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1030 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1035 .cmd_rcgr = 0x1600c,
1049 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1050 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1051 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1052 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1057 .cmd_rcgr = 0x77024,
1071 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1072 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1073 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1078 .cmd_rcgr = 0x7706c,
1079 .mnd_width = 0,
1092 .cmd_rcgr = 0x770a0,
1093 .mnd_width = 0,
1106 .cmd_rcgr = 0x77084,
1107 .mnd_width = 0,
1120 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1121 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1122 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1123 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1128 .cmd_rcgr = 0xf020,
1142 F(19200000, P_BI_TCXO, 1, 0, 0),
1147 .cmd_rcgr = 0xf038,
1148 .mnd_width = 0,
1161 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1162 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1167 .cmd_rcgr = 0x9e020,
1181 .cmd_rcgr = 0x9e038,
1182 .mnd_width = 0,
1195 .cmd_rcgr = 0xf064,
1196 .mnd_width = 0,
1209 .cmd_rcgr = 0x9e064,
1210 .mnd_width = 0,
1223 F(4800000, P_BI_TCXO, 4, 0, 0),
1224 F(19200000, P_BI_TCXO, 1, 0, 0),
1229 .cmd_rcgr = 0x3d02c,
1230 .mnd_width = 0,
1243 .reg = 0x48024,
1244 .shift = 0,
1258 .reg = 0xf050,
1259 .shift = 0,
1273 .reg = 0x9e050,
1274 .shift = 0,
1288 .halt_reg = 0x8c004,
1291 .enable_reg = 0x8c004,
1292 .enable_mask = BIT(0),
1301 .halt_reg = 0x8c008,
1304 .enable_reg = 0x8c008,
1305 .enable_mask = BIT(0),
1314 .halt_reg = 0x6b080,
1316 .hwcg_reg = 0x6b080,
1319 .enable_reg = 0x52000,
1329 .halt_reg = 0x8d084,
1331 .hwcg_reg = 0x8d084,
1334 .enable_reg = 0x52000,
1344 .halt_reg = 0x90010,
1346 .hwcg_reg = 0x90010,
1349 .enable_reg = 0x52000,
1359 .halt_reg = 0x8d088,
1361 .hwcg_reg = 0x8d088,
1364 .enable_reg = 0x52008,
1374 .halt_reg = 0x770cc,
1376 .hwcg_reg = 0x770cc,
1379 .enable_reg = 0x770cc,
1380 .enable_mask = BIT(0),
1394 .halt_reg = 0xf080,
1396 .hwcg_reg = 0xf080,
1399 .enable_reg = 0xf080,
1400 .enable_mask = BIT(0),
1414 .halt_reg = 0x9e080,
1416 .hwcg_reg = 0x9e080,
1419 .enable_reg = 0x9e080,
1420 .enable_mask = BIT(0),
1434 .halt_reg = 0x26010,
1436 .hwcg_reg = 0x26010,
1439 .enable_reg = 0x26010,
1440 .enable_mask = BIT(0),
1449 .halt_reg = 0x2601c,
1451 .hwcg_reg = 0x2601c,
1454 .enable_reg = 0x2601c,
1455 .enable_mask = BIT(0),
1464 .halt_reg = 0xf07c,
1466 .hwcg_reg = 0xf07c,
1469 .enable_reg = 0xf07c,
1470 .enable_mask = BIT(0),
1484 .halt_reg = 0x9e07c,
1486 .hwcg_reg = 0x9e07c,
1489 .enable_reg = 0x9e07c,
1490 .enable_mask = BIT(0),
1505 .halt_reg = 0x48000,
1507 .hwcg_reg = 0x48000,
1510 .enable_reg = 0x52000,
1525 .halt_reg = 0x71154,
1527 .hwcg_reg = 0x71154,
1530 .enable_reg = 0x71154,
1531 .enable_mask = BIT(0),
1540 .halt_reg = 0x8d080,
1542 .hwcg_reg = 0x8d080,
1545 .enable_reg = 0x52000,
1557 .enable_reg = 0x52000,
1572 .halt_reg = 0x2700c,
1574 .hwcg_reg = 0x2700c,
1577 .enable_reg = 0x2700c,
1578 .enable_mask = BIT(0),
1587 .halt_reg = 0x27014,
1589 .hwcg_reg = 0x27014,
1592 .enable_reg = 0x27014,
1593 .enable_mask = BIT(0),
1602 .halt_reg = 0x64000,
1605 .enable_reg = 0x64000,
1606 .enable_mask = BIT(0),
1620 .halt_reg = 0x65000,
1623 .enable_reg = 0x65000,
1624 .enable_mask = BIT(0),
1638 .halt_reg = 0x66000,
1641 .enable_reg = 0x66000,
1642 .enable_mask = BIT(0),
1658 .enable_reg = 0x52000,
1675 .enable_reg = 0x52000,
1690 .halt_reg = 0x8c014,
1693 .enable_reg = 0x8c014,
1694 .enable_mask = BIT(0),
1703 .halt_reg = 0x7100c,
1705 .hwcg_reg = 0x7100c,
1708 .enable_reg = 0x7100c,
1709 .enable_mask = BIT(0),
1718 .halt_reg = 0x71018,
1721 .enable_reg = 0x71018,
1722 .enable_mask = BIT(0),
1731 .halt_reg = 0x6b038,
1734 .enable_reg = 0x52000,
1749 .halt_reg = 0x8d038,
1752 .enable_reg = 0x52000,
1767 .halt_reg = 0x6b028,
1770 .enable_reg = 0x52008,
1785 .halt_reg = 0x6b024,
1787 .hwcg_reg = 0x6b024,
1790 .enable_reg = 0x52008,
1800 .halt_reg = 0x6b01c,
1803 .enable_reg = 0x52008,
1813 .halt_reg = 0x6b030,
1816 .enable_reg = 0x52008,
1831 .halt_reg = 0x6b014,
1834 .enable_reg = 0x52008,
1835 .enable_mask = BIT(0),
1844 .halt_reg = 0x6b010,
1847 .enable_reg = 0x52008,
1857 .halt_reg = 0x8d028,
1860 .enable_reg = 0x52000,
1875 .halt_reg = 0x8d024,
1877 .hwcg_reg = 0x8d024,
1880 .enable_reg = 0x52000,
1890 .halt_reg = 0x8d01c,
1893 .enable_reg = 0x52000,
1903 .halt_reg = 0x8d030,
1906 .enable_reg = 0x52000,
1921 .halt_reg = 0x8d014,
1924 .enable_reg = 0x52000,
1934 .halt_reg = 0x8d010,
1937 .enable_reg = 0x52000,
1947 .halt_reg = 0x90018,
1949 .hwcg_reg = 0x90018,
1952 .enable_reg = 0x52000,
1962 .halt_reg = 0x3300c,
1965 .enable_reg = 0x3300c,
1966 .enable_mask = BIT(0),
1980 .halt_reg = 0x33004,
1982 .hwcg_reg = 0x33004,
1985 .enable_reg = 0x33004,
1986 .enable_mask = BIT(0),
1995 .halt_reg = 0x33008,
1998 .enable_reg = 0x33008,
1999 .enable_mask = BIT(0),
2008 .halt_reg = 0x26008,
2010 .hwcg_reg = 0x26008,
2013 .enable_reg = 0x26008,
2014 .enable_mask = BIT(0),
2023 .halt_reg = 0x2600c,
2025 .hwcg_reg = 0x2600c,
2028 .enable_reg = 0x2600c,
2029 .enable_mask = BIT(0),
2038 .halt_reg = 0x27008,
2041 .enable_reg = 0x27008,
2042 .enable_mask = BIT(0),
2051 .halt_reg = 0x28008,
2053 .hwcg_reg = 0x28008,
2056 .enable_reg = 0x28008,
2057 .enable_mask = BIT(0),
2066 .halt_reg = 0x4b004,
2068 .hwcg_reg = 0x4b004,
2071 .enable_reg = 0x4b004,
2072 .enable_mask = BIT(0),
2081 .halt_reg = 0x4b008,
2084 .enable_reg = 0x4b008,
2085 .enable_mask = BIT(0),
2099 .halt_reg = 0x23008,
2102 .enable_reg = 0x52008,
2112 .halt_reg = 0x23000,
2115 .enable_reg = 0x52008,
2125 .halt_reg = 0x1700c,
2128 .enable_reg = 0x52008,
2143 .halt_reg = 0x1713c,
2146 .enable_reg = 0x52008,
2161 .halt_reg = 0x1726c,
2164 .enable_reg = 0x52008,
2179 .halt_reg = 0x1739c,
2182 .enable_reg = 0x52008,
2197 .halt_reg = 0x174cc,
2200 .enable_reg = 0x52008,
2215 .halt_reg = 0x175fc,
2218 .enable_reg = 0x52008,
2233 .halt_reg = 0x1772c,
2236 .enable_reg = 0x52008,
2251 .halt_reg = 0x1785c,
2254 .enable_reg = 0x52008,
2269 .halt_reg = 0x23140,
2272 .enable_reg = 0x52008,
2282 .halt_reg = 0x23138,
2285 .enable_reg = 0x52008,
2295 .halt_reg = 0x1800c,
2298 .enable_reg = 0x52008,
2313 .halt_reg = 0x1813c,
2316 .enable_reg = 0x52008,
2331 .halt_reg = 0x1826c,
2334 .enable_reg = 0x52008,
2349 .halt_reg = 0x1839c,
2352 .enable_reg = 0x52008,
2367 .halt_reg = 0x184cc,
2370 .enable_reg = 0x52008,
2385 .halt_reg = 0x185fc,
2388 .enable_reg = 0x52008,
2403 .halt_reg = 0x1872c,
2406 .enable_reg = 0x52000,
2421 .halt_reg = 0x1885c,
2424 .enable_reg = 0x52000,
2439 .halt_reg = 0x17004,
2441 .hwcg_reg = 0x17004,
2444 .enable_reg = 0x52008,
2454 .halt_reg = 0x17008,
2456 .hwcg_reg = 0x17008,
2459 .enable_reg = 0x52008,
2469 .halt_reg = 0x18004,
2471 .hwcg_reg = 0x18004,
2474 .enable_reg = 0x52008,
2484 .halt_reg = 0x18008,
2486 .hwcg_reg = 0x18008,
2489 .enable_reg = 0x52008,
2499 .halt_reg = 0x75004,
2502 .enable_reg = 0x75004,
2503 .enable_mask = BIT(0),
2512 .halt_reg = 0x75008,
2515 .enable_reg = 0x75008,
2516 .enable_mask = BIT(0),
2530 .halt_reg = 0x75024,
2532 .hwcg_reg = 0x75024,
2535 .enable_reg = 0x75024,
2536 .enable_mask = BIT(0),
2550 .halt_reg = 0x14008,
2553 .enable_reg = 0x14008,
2554 .enable_mask = BIT(0),
2563 .halt_reg = 0x14004,
2566 .enable_reg = 0x14004,
2567 .enable_mask = BIT(0),
2581 .halt_reg = 0x16008,
2584 .enable_reg = 0x16008,
2585 .enable_mask = BIT(0),
2594 .halt_reg = 0x16004,
2597 .enable_reg = 0x16004,
2598 .enable_mask = BIT(0),
2613 .halt_reg = 0x48178,
2615 .hwcg_reg = 0x48178,
2618 .enable_reg = 0x52000,
2619 .enable_mask = BIT(0),
2633 .halt_reg = 0x9001c,
2636 .enable_reg = 0x9001c,
2637 .enable_mask = BIT(0),
2646 .halt_reg = 0x26024,
2648 .hwcg_reg = 0x26024,
2651 .enable_reg = 0x26024,
2652 .enable_mask = BIT(0),
2661 .halt_reg = 0x26018,
2663 .hwcg_reg = 0x26018,
2666 .enable_reg = 0x26018,
2667 .enable_mask = BIT(0),
2676 .halt_reg = 0x8c000,
2679 .enable_reg = 0x8c000,
2680 .enable_mask = BIT(0),
2689 .halt_reg = 0x77018,
2691 .hwcg_reg = 0x77018,
2694 .enable_reg = 0x77018,
2695 .enable_mask = BIT(0),
2704 .halt_reg = 0x77010,
2706 .hwcg_reg = 0x77010,
2709 .enable_reg = 0x77010,
2710 .enable_mask = BIT(0),
2724 .halt_reg = 0x77064,
2726 .hwcg_reg = 0x77064,
2729 .enable_reg = 0x77064,
2730 .enable_mask = BIT(0),
2744 .halt_reg = 0x7709c,
2746 .hwcg_reg = 0x7709c,
2749 .enable_reg = 0x7709c,
2750 .enable_mask = BIT(0),
2764 .halt_reg = 0x77020,
2767 .enable_reg = 0x77020,
2768 .enable_mask = BIT(0),
2782 .halt_reg = 0x770b8,
2785 .enable_reg = 0x770b8,
2786 .enable_mask = BIT(0),
2800 .halt_reg = 0x7701c,
2803 .enable_reg = 0x7701c,
2804 .enable_mask = BIT(0),
2818 .halt_reg = 0x7705c,
2820 .hwcg_reg = 0x7705c,
2823 .enable_reg = 0x7705c,
2824 .enable_mask = BIT(0),
2838 .halt_reg = 0xf010,
2841 .enable_reg = 0xf010,
2842 .enable_mask = BIT(0),
2856 .halt_reg = 0xf01c,
2859 .enable_reg = 0xf01c,
2860 .enable_mask = BIT(0),
2875 .halt_reg = 0xf018,
2878 .enable_reg = 0xf018,
2879 .enable_mask = BIT(0),
2888 .halt_reg = 0x9e010,
2891 .enable_reg = 0x9e010,
2892 .enable_mask = BIT(0),
2906 .halt_reg = 0x9e01c,
2909 .enable_reg = 0x9e01c,
2910 .enable_mask = BIT(0),
2925 .halt_reg = 0x9e018,
2928 .enable_reg = 0x9e018,
2929 .enable_mask = BIT(0),
2938 .halt_reg = 0xf054,
2941 .enable_reg = 0xf054,
2942 .enable_mask = BIT(0),
2956 .halt_reg = 0xf058,
2959 .enable_reg = 0xf058,
2960 .enable_mask = BIT(0),
2974 .halt_reg = 0xf05c,
2976 .hwcg_reg = 0xf05c,
2979 .enable_reg = 0xf05c,
2980 .enable_mask = BIT(0),
2994 .halt_reg = 0x47020,
2997 .enable_reg = 0x47020,
2998 .enable_mask = BIT(0),
3006 .halt_reg = 0x8a000,
3009 .enable_reg = 0x8a000,
3010 .enable_mask = BIT(0),
3019 .halt_reg = 0x8a004,
3022 .enable_reg = 0x8a004,
3023 .enable_mask = BIT(0),
3032 .halt_reg = 0x8a154,
3035 .enable_reg = 0x8a154,
3036 .enable_mask = BIT(0),
3045 .halt_reg = 0x8a158,
3048 .enable_reg = 0x8a158,
3049 .enable_mask = BIT(0),
3058 .reg = 0x8a2a4,
3059 .shift = 0,
3073 .halt_reg = 0x9e054,
3076 .enable_reg = 0x9e054,
3077 .enable_mask = BIT(0),
3091 .halt_reg = 0x9e058,
3094 .enable_reg = 0x9e058,
3095 .enable_mask = BIT(0),
3109 .halt_reg = 0x9e05c,
3111 .hwcg_reg = 0x9e05c,
3114 .enable_reg = 0x9e05c,
3115 .enable_mask = BIT(0),
3129 .halt_reg = 0x2800c,
3131 .hwcg_reg = 0x2800c,
3134 .enable_reg = 0x2800c,
3135 .enable_mask = BIT(0),
3144 .halt_reg = 0x28010,
3146 .hwcg_reg = 0x28010,
3149 .enable_reg = 0x28010,
3150 .enable_mask = BIT(0),
3159 .halt_reg = 0x9d154,
3162 .enable_reg = 0x9d154,
3163 .enable_mask = BIT(0),
3172 .halt_reg = 0x9d158,
3175 .enable_reg = 0x9d158,
3176 .enable_mask = BIT(0),
3185 .halt_reg = 0x9d16c,
3188 .enable_reg = 0x9d16c,
3189 .enable_mask = BIT(0),
3198 .gdscr = 0x6b004,
3207 .gdscr = 0x8d004,
3216 .gdscr = 0x77004,
3225 .gdscr = 0xf004,
3234 .gdscr = 0x9e004,
3243 .gdscr = 0x7d050,
3252 .gdscr = 0x7d058,
3261 .gdscr = 0x7d054,
3270 .gdscr = 0x7d05c,
3279 .gdscr = 0x7d060,
3492 [GCC_PCIE_0_BCR] = { 0x6b000 },
3493 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3494 [GCC_PCIE_1_BCR] = { 0x8d000 },
3495 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3496 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3497 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3498 [GCC_SDCC1_BCR] = { 0x75000 },
3499 [GCC_SDCC2_BCR] = { 0x14000 },
3500 [GCC_SDCC4_BCR] = { 0x16000 },
3501 [GCC_UFS_PHY_BCR] = { 0x77000 },
3502 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3503 [GCC_USB30_SEC_BCR] = { 0x9e000 },
3504 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3505 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3506 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3507 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3533 .max_register = 0x9f128,
3567 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); in gcc_sc7280_probe()
3568 regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); in gcc_sc7280_probe()
3569 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); in gcc_sc7280_probe()
3570 regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); in gcc_sc7280_probe()
3571 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); in gcc_sc7280_probe()
3572 regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); in gcc_sc7280_probe()
3573 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc7280_probe()