Lines Matching +full:0 +full:x6a000
37 .offset = 0x0,
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
55 { 0x1, 2 },
60 .offset = 0x0,
90 .offset = 0x01000,
93 .enable_reg = 0x52010,
108 .offset = 0x76000,
111 .enable_reg = 0x52010,
126 .offset = 0x13000,
129 .enable_reg = 0x52010,
144 .offset = 0x27000,
147 .enable_reg = 0x52010,
162 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
199 { P_BI_TCXO, 0 },
217 { P_BI_TCXO, 0 },
229 { P_BI_TCXO, 0 },
245 { P_BI_TCXO, 0 },
261 { P_BI_TCXO, 0 },
275 F(19200000, P_BI_TCXO, 1, 0, 0),
280 .cmd_rcgr = 0x48014,
281 .mnd_width = 0,
295 F(19200000, P_BI_TCXO, 1, 0, 0),
296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
304 .cmd_rcgr = 0x64004,
318 .cmd_rcgr = 0x65004,
332 .cmd_rcgr = 0x66004,
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
352 .cmd_rcgr = 0x33010,
353 .mnd_width = 0,
366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
373 .cmd_rcgr = 0x4b00c,
374 .mnd_width = 0,
389 F(19200000, P_BI_TCXO, 1, 0, 0),
393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
415 .cmd_rcgr = 0x17034,
431 .cmd_rcgr = 0x17164,
447 .cmd_rcgr = 0x17294,
463 .cmd_rcgr = 0x173c4,
479 .cmd_rcgr = 0x174f4,
495 .cmd_rcgr = 0x17624,
511 .cmd_rcgr = 0x18018,
527 .cmd_rcgr = 0x18148,
543 .cmd_rcgr = 0x18278,
559 .cmd_rcgr = 0x183a8,
575 .cmd_rcgr = 0x184d8,
591 .cmd_rcgr = 0x18608,
603 F(19200000, P_BI_TCXO, 1, 0, 0),
606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
614 .cmd_rcgr = 0x12028,
628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
636 .cmd_rcgr = 0x12010,
637 .mnd_width = 0,
651 F(9600000, P_BI_TCXO, 2, 0, 0),
652 F(19200000, P_BI_TCXO, 1, 0, 0),
653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
654 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
655 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
656 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
661 .cmd_rcgr = 0x1400c,
675 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
676 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
677 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
678 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
679 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
684 .cmd_rcgr = 0x77020,
698 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
699 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
700 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
701 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
706 .cmd_rcgr = 0x77048,
707 .mnd_width = 0,
720 F(9600000, P_BI_TCXO, 2, 0, 0),
721 F(19200000, P_BI_TCXO, 1, 0, 0),
726 .cmd_rcgr = 0x77098,
727 .mnd_width = 0,
740 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
741 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
742 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
747 .cmd_rcgr = 0x77060,
748 .mnd_width = 0,
761 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
762 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
763 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
764 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
769 .cmd_rcgr = 0xf01c,
783 F(19200000, P_BI_TCXO, 1, 0, 0),
784 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
789 .cmd_rcgr = 0xf034,
790 .mnd_width = 0,
803 F(19200000, P_BI_TCXO, 1, 0, 0),
808 .cmd_rcgr = 0xf060,
809 .mnd_width = 0,
822 F(4800000, P_BI_TCXO, 4, 0, 0),
823 F(19200000, P_BI_TCXO, 1, 0, 0),
828 .cmd_rcgr = 0x3d030,
829 .mnd_width = 0,
842 .halt_reg = 0x82024,
844 .hwcg_reg = 0x82024,
847 .enable_reg = 0x82024,
848 .enable_mask = BIT(0),
862 .halt_reg = 0x8201c,
865 .enable_reg = 0x8201c,
866 .enable_mask = BIT(0),
880 .halt_reg = 0x38004,
882 .hwcg_reg = 0x38004,
885 .enable_reg = 0x52000,
895 .halt_reg = 0xb020,
898 .enable_reg = 0xb020,
899 .enable_mask = BIT(0),
908 .halt_reg = 0xb080,
910 .hwcg_reg = 0xb080,
913 .enable_reg = 0xb080,
914 .enable_mask = BIT(0),
923 .halt_reg = 0x4100c,
925 .hwcg_reg = 0x4100c,
928 .enable_reg = 0x52000,
938 .halt_reg = 0x41008,
941 .enable_reg = 0x52000,
951 .halt_reg = 0x41004,
954 .enable_reg = 0x52000,
964 .halt_reg = 0x502c,
967 .enable_reg = 0x502c,
968 .enable_mask = BIT(0),
983 .halt_reg = 0x48000,
986 .enable_reg = 0x52000,
1001 .halt_reg = 0x48008,
1004 .enable_reg = 0x48008,
1005 .enable_mask = BIT(0),
1014 .halt_reg = 0x4452c,
1017 .enable_reg = 0x4452c,
1018 .enable_mask = BIT(0),
1029 .enable_reg = 0x52000,
1045 .enable_reg = 0x52000,
1059 .halt_reg = 0xb024,
1062 .enable_reg = 0xb024,
1063 .enable_mask = BIT(0),
1072 .halt_reg = 0xb084,
1074 .hwcg_reg = 0xb084,
1077 .enable_reg = 0xb084,
1078 .enable_mask = BIT(0),
1087 .halt_reg = 0x64000,
1090 .enable_reg = 0x64000,
1091 .enable_mask = BIT(0),
1105 .halt_reg = 0x65000,
1108 .enable_reg = 0x65000,
1109 .enable_mask = BIT(0),
1123 .halt_reg = 0x66000,
1126 .enable_reg = 0x66000,
1127 .enable_mask = BIT(0),
1143 .enable_reg = 0x52000,
1159 .enable_reg = 0x52000,
1173 .halt_reg = 0x7100c,
1176 .enable_reg = 0x7100c,
1177 .enable_mask = BIT(0),
1186 .halt_reg = 0x71018,
1189 .enable_reg = 0x71018,
1190 .enable_mask = BIT(0),
1199 .halt_reg = 0x4d008,
1202 .enable_reg = 0x4d008,
1203 .enable_mask = BIT(0),
1212 .halt_reg = 0x73008,
1215 .enable_reg = 0x73008,
1216 .enable_mask = BIT(0),
1225 .halt_reg = 0x73018,
1228 .enable_reg = 0x73018,
1229 .enable_mask = BIT(0),
1238 .halt_reg = 0x7301c,
1241 .enable_reg = 0x7301c,
1242 .enable_mask = BIT(0),
1251 .halt_reg = 0x4d004,
1253 .hwcg_reg = 0x4d004,
1256 .enable_reg = 0x4d004,
1257 .enable_mask = BIT(0),
1266 .halt_reg = 0x4d1a0,
1268 .hwcg_reg = 0x4d1a0,
1271 .enable_reg = 0x4d1a0,
1272 .enable_mask = BIT(0),
1283 .enable_reg = 0x52000,
1299 .enable_reg = 0x52000,
1314 .halt_reg = 0x3300c,
1317 .enable_reg = 0x3300c,
1318 .enable_mask = BIT(0),
1332 .halt_reg = 0x33004,
1334 .hwcg_reg = 0x33004,
1337 .enable_reg = 0x33004,
1338 .enable_mask = BIT(0),
1347 .halt_reg = 0x33008,
1350 .enable_reg = 0x33008,
1351 .enable_mask = BIT(0),
1360 .halt_reg = 0x34004,
1362 .hwcg_reg = 0x34004,
1365 .enable_reg = 0x52000,
1375 .halt_reg = 0x4b004,
1377 .hwcg_reg = 0x4b004,
1380 .enable_reg = 0x4b004,
1381 .enable_mask = BIT(0),
1390 .halt_reg = 0x4b008,
1393 .enable_reg = 0x4b008,
1394 .enable_mask = BIT(0),
1408 .halt_reg = 0x17014,
1411 .enable_reg = 0x52008,
1421 .halt_reg = 0x1700c,
1424 .enable_reg = 0x52008,
1434 .halt_reg = 0x17030,
1437 .enable_reg = 0x52008,
1452 .halt_reg = 0x17160,
1455 .enable_reg = 0x52008,
1470 .halt_reg = 0x17290,
1473 .enable_reg = 0x52008,
1488 .halt_reg = 0x173c0,
1491 .enable_reg = 0x52008,
1506 .halt_reg = 0x174f0,
1509 .enable_reg = 0x52008,
1524 .halt_reg = 0x17620,
1527 .enable_reg = 0x52008,
1542 .halt_reg = 0x18004,
1545 .enable_reg = 0x52008,
1555 .halt_reg = 0x18008,
1558 .enable_reg = 0x52008,
1568 .halt_reg = 0x18014,
1571 .enable_reg = 0x52008,
1586 .halt_reg = 0x18144,
1589 .enable_reg = 0x52008,
1604 .halt_reg = 0x18274,
1607 .enable_reg = 0x52008,
1622 .halt_reg = 0x183a4,
1625 .enable_reg = 0x52008,
1640 .halt_reg = 0x184d4,
1643 .enable_reg = 0x52008,
1658 .halt_reg = 0x18604,
1661 .enable_reg = 0x52008,
1676 .halt_reg = 0x17004,
1679 .enable_reg = 0x52008,
1689 .halt_reg = 0x17008,
1691 .hwcg_reg = 0x17008,
1694 .enable_reg = 0x52008,
1704 .halt_reg = 0x1800c,
1707 .enable_reg = 0x52008,
1717 .halt_reg = 0x18010,
1719 .hwcg_reg = 0x18010,
1722 .enable_reg = 0x52008,
1732 .halt_reg = 0x12008,
1735 .enable_reg = 0x12008,
1736 .enable_mask = BIT(0),
1745 .halt_reg = 0x1200c,
1748 .enable_reg = 0x1200c,
1749 .enable_mask = BIT(0),
1763 .halt_reg = 0x12040,
1766 .enable_reg = 0x12040,
1767 .enable_mask = BIT(0),
1781 .halt_reg = 0x14008,
1784 .enable_reg = 0x14008,
1785 .enable_mask = BIT(0),
1794 .halt_reg = 0x14004,
1797 .enable_reg = 0x14004,
1798 .enable_mask = BIT(0),
1813 .halt_reg = 0x4144,
1816 .enable_reg = 0x52000,
1817 .enable_mask = BIT(0),
1831 .halt_reg = 0x8c000,
1834 .enable_reg = 0x8c000,
1835 .enable_mask = BIT(0),
1844 .halt_reg = 0x77014,
1846 .hwcg_reg = 0x77014,
1849 .enable_reg = 0x77014,
1850 .enable_mask = BIT(0),
1859 .halt_reg = 0x77038,
1861 .hwcg_reg = 0x77038,
1864 .enable_reg = 0x77038,
1865 .enable_mask = BIT(0),
1879 .halt_reg = 0x77090,
1881 .hwcg_reg = 0x77090,
1884 .enable_reg = 0x77090,
1885 .enable_mask = BIT(0),
1899 .halt_reg = 0x77094,
1901 .hwcg_reg = 0x77094,
1904 .enable_reg = 0x77094,
1905 .enable_mask = BIT(0),
1919 .halt_reg = 0x7701c,
1922 .enable_reg = 0x7701c,
1923 .enable_mask = BIT(0),
1932 .halt_reg = 0x77018,
1935 .enable_reg = 0x77018,
1936 .enable_mask = BIT(0),
1945 .halt_reg = 0x7708c,
1947 .hwcg_reg = 0x7708c,
1950 .enable_reg = 0x7708c,
1951 .enable_mask = BIT(0),
1965 .halt_reg = 0xf010,
1968 .enable_reg = 0xf010,
1969 .enable_mask = BIT(0),
1983 .halt_reg = 0xf018,
1986 .enable_reg = 0xf018,
1987 .enable_mask = BIT(0),
2002 .halt_reg = 0xf014,
2005 .enable_reg = 0xf014,
2006 .enable_mask = BIT(0),
2015 .halt_reg = 0x8c010,
2018 .enable_reg = 0x8c010,
2019 .enable_mask = BIT(0),
2028 .halt_reg = 0xf050,
2031 .enable_reg = 0xf050,
2032 .enable_mask = BIT(0),
2046 .halt_reg = 0xf054,
2049 .enable_reg = 0xf054,
2050 .enable_mask = BIT(0),
2064 .halt_reg = 0xf058,
2067 .enable_reg = 0xf058,
2068 .enable_mask = BIT(0),
2077 .halt_reg = 0x6a004,
2079 .hwcg_reg = 0x6a004,
2082 .enable_reg = 0x6a004,
2083 .enable_mask = BIT(0),
2092 .halt_reg = 0xb01c,
2095 .enable_reg = 0xb01c,
2096 .enable_mask = BIT(0),
2107 .enable_reg = 0x52000,
2122 .halt_reg = 0xb07c,
2124 .hwcg_reg = 0xb07c,
2127 .enable_reg = 0xb07c,
2128 .enable_mask = BIT(0),
2137 .halt_reg = 0x8a000,
2140 .enable_reg = 0x8a000,
2141 .enable_mask = BIT(0),
2150 .halt_reg = 0x8a004,
2153 .enable_reg = 0x8a004,
2154 .enable_mask = BIT(0),
2163 .halt_reg = 0x8a00c,
2166 .enable_reg = 0x8a00c,
2167 .enable_mask = BIT(0),
2176 .halt_reg = 0x8a150,
2179 .enable_reg = 0x8a150,
2180 .enable_mask = BIT(0),
2189 .halt_reg = 0x8a154,
2192 .enable_reg = 0x8a154,
2193 .enable_mask = BIT(0),
2202 .halt_reg = 0x47018,
2205 .enable_reg = 0x47018,
2206 .enable_mask = BIT(0),
2215 .gdscr = 0x77004,
2223 .gdscr = 0x0f004,
2231 .gdscr = 0x7d040,
2240 .gdscr = 0x7d044,
2391 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2392 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2393 [GCC_UFS_PHY_BCR] = { 0x77000 },
2394 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2395 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2396 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2397 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2398 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2399 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2400 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2401 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2423 .max_register = 0x18208c,
2458 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sc7180_probe()
2459 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc7180_probe()
2460 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc7180_probe()
2467 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); in gcc_sc7180_probe()
2468 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); in gcc_sc7180_probe()
2469 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); in gcc_sc7180_probe()
2470 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); in gcc_sc7180_probe()
2471 regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); in gcc_sc7180_probe()
2472 regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); in gcc_sc7180_probe()
2473 regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); in gcc_sc7180_probe()
2474 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc7180_probe()