Lines Matching +full:0 +full:x2d000
39 { P_XO, 0 },
53 { P_XO, 0 },
65 { P_XO, 0 },
81 { P_XO, 0 },
93 { P_XO, 0 },
107 { P_XO, 0 },
132 { 250000000, 2000000000, 0 },
137 .offset = 0x0,
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
154 .offset = 0x0,
165 .offset = 0x0,
176 .offset = 0x0,
187 .offset = 0x0,
198 .offset = 0x1000,
203 .enable_reg = 0x52000,
215 .offset = 0x1000,
226 .offset = 0x1000,
237 .offset = 0x1000,
248 .offset = 0x1000,
259 .offset = 0x2000,
264 .enable_reg = 0x52000,
276 .offset = 0x2000,
287 .offset = 0x2000,
298 .offset = 0x2000,
309 .offset = 0x2000,
320 .offset = 0x3000,
325 .enable_reg = 0x52000,
337 .offset = 0x3000,
348 .offset = 0x3000,
359 .offset = 0x3000,
370 .offset = 0x3000,
381 .offset = 0x77000,
386 .enable_reg = 0x52000,
398 .offset = 0x77000,
409 .offset = 0x77000,
420 .offset = 0x77000,
431 .offset = 0x77000,
442 F(19200000, P_XO, 1, 0, 0),
443 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
448 .cmd_rcgr = 0x19020,
449 .mnd_width = 0,
463 F(4800000, P_XO, 4, 0, 0),
464 F(9600000, P_XO, 2, 0, 0),
466 F(19200000, P_XO, 1, 0, 0),
468 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
473 .cmd_rcgr = 0x1900c,
487 .cmd_rcgr = 0x1b020,
488 .mnd_width = 0,
501 .cmd_rcgr = 0x1b00c,
515 .cmd_rcgr = 0x1d020,
516 .mnd_width = 0,
529 .cmd_rcgr = 0x1d00c,
543 .cmd_rcgr = 0x1f020,
544 .mnd_width = 0,
557 .cmd_rcgr = 0x1f00c,
571 .cmd_rcgr = 0x21020,
572 .mnd_width = 0,
585 .cmd_rcgr = 0x2100c,
599 .cmd_rcgr = 0x23020,
600 .mnd_width = 0,
613 .cmd_rcgr = 0x2300c,
631 F(19200000, P_XO, 1, 0, 0),
634 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
636 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
640 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
641 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
646 .cmd_rcgr = 0x1a00c,
660 .cmd_rcgr = 0x1c00c,
674 .cmd_rcgr = 0x1e00c,
688 .cmd_rcgr = 0x26020,
689 .mnd_width = 0,
702 .cmd_rcgr = 0x2600c,
716 .cmd_rcgr = 0x28020,
717 .mnd_width = 0,
730 .cmd_rcgr = 0x2800c,
744 .cmd_rcgr = 0x2a020,
745 .mnd_width = 0,
758 .cmd_rcgr = 0x2a00c,
772 .cmd_rcgr = 0x2c020,
773 .mnd_width = 0,
786 .cmd_rcgr = 0x2c00c,
800 .cmd_rcgr = 0x2e020,
801 .mnd_width = 0,
814 .cmd_rcgr = 0x2e00c,
828 .cmd_rcgr = 0x30020,
829 .mnd_width = 0,
842 .cmd_rcgr = 0x3000c,
856 .cmd_rcgr = 0x2700c,
870 .cmd_rcgr = 0x2900c,
884 .cmd_rcgr = 0x2b00c,
898 F(19200000, P_XO, 1, 0, 0),
899 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
900 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
905 .cmd_rcgr = 0x64004,
919 .cmd_rcgr = 0x65004,
933 .cmd_rcgr = 0x66004,
947 F(19200000, P_XO, 1, 0, 0),
948 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
949 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
954 .cmd_rcgr = 0x48014,
955 .mnd_width = 0,
968 F(19200000, P_XO, 1, 0, 0),
973 .cmd_rcgr = 0x48044,
974 .mnd_width = 0,
992 .cmd_rcgr = 0x6c000,
1006 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1011 .cmd_rcgr = 0x33010,
1012 .mnd_width = 0,
1029 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1030 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1031 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1036 .cmd_rcgr = 0x14010,
1054 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1055 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1060 .cmd_rcgr = 0x16010,
1079 .cmd_rcgr = 0x36010,
1093 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1094 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1095 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1100 .cmd_rcgr = 0x75018,
1114 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1115 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1116 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1121 .cmd_rcgr = 0x76028,
1135 F(19200000, P_XO, 1, 0, 0),
1136 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1137 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1138 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1143 .cmd_rcgr = 0xf014,
1157 .cmd_rcgr = 0xf028,
1158 .mnd_width = 0,
1171 F(1200000, P_XO, 16, 0, 0),
1176 .cmd_rcgr = 0x5000c,
1177 .mnd_width = 0,
1190 .halt_reg = 0x8202c,
1193 .enable_reg = 0x8202c,
1194 .enable_mask = BIT(0),
1203 .halt_reg = 0x82028,
1206 .enable_reg = 0x82028,
1207 .enable_mask = BIT(0),
1221 .halt_reg = 0x82024,
1224 .enable_reg = 0x82024,
1225 .enable_mask = BIT(0),
1239 .halt_reg = 0x48090,
1242 .enable_reg = 0x48090,
1243 .enable_mask = BIT(0),
1252 .halt_reg = 0x48094,
1255 .enable_reg = 0x48094,
1256 .enable_mask = BIT(0),
1265 .halt_reg = 0x48004,
1268 .enable_reg = 0x52004,
1278 .halt_reg = 0x4401c,
1281 .enable_reg = 0x4401c,
1282 .enable_mask = BIT(0),
1291 .halt_reg = 0x8a000,
1294 .enable_reg = 0x8a000,
1295 .enable_mask = BIT(0),
1304 .halt_reg = 0x8a03c,
1307 .enable_reg = 0x8a03c,
1308 .enable_mask = BIT(0),
1317 .halt_reg = 0x8a004,
1320 .enable_reg = 0x8a004,
1321 .enable_mask = BIT(0),
1330 .halt_reg = 0x38004,
1332 .hwcg_reg = 0x38004,
1335 .enable_reg = 0x52004,
1347 .enable_reg = 0x5200c,
1363 .enable_reg = 0x5200c,
1373 .halt_reg = 0x17004,
1376 .enable_reg = 0x52004,
1386 .halt_reg = 0x19008,
1389 .enable_reg = 0x19008,
1390 .enable_mask = BIT(0),
1404 .halt_reg = 0x19004,
1407 .enable_reg = 0x19004,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0x1b008,
1425 .enable_reg = 0x1b008,
1426 .enable_mask = BIT(0),
1440 .halt_reg = 0x1b004,
1443 .enable_reg = 0x1b004,
1444 .enable_mask = BIT(0),
1458 .halt_reg = 0x1d008,
1461 .enable_reg = 0x1d008,
1462 .enable_mask = BIT(0),
1476 .halt_reg = 0x1d004,
1479 .enable_reg = 0x1d004,
1480 .enable_mask = BIT(0),
1494 .halt_reg = 0x1f008,
1497 .enable_reg = 0x1f008,
1498 .enable_mask = BIT(0),
1512 .halt_reg = 0x1f004,
1515 .enable_reg = 0x1f004,
1516 .enable_mask = BIT(0),
1530 .halt_reg = 0x21008,
1533 .enable_reg = 0x21008,
1534 .enable_mask = BIT(0),
1548 .halt_reg = 0x21004,
1551 .enable_reg = 0x21004,
1552 .enable_mask = BIT(0),
1566 .halt_reg = 0x23008,
1569 .enable_reg = 0x23008,
1570 .enable_mask = BIT(0),
1584 .halt_reg = 0x23004,
1587 .enable_reg = 0x23004,
1588 .enable_mask = BIT(0),
1602 .halt_reg = 0x17008,
1605 .enable_reg = 0x52004,
1615 .halt_reg = 0x1a004,
1618 .enable_reg = 0x1a004,
1619 .enable_mask = BIT(0),
1633 .halt_reg = 0x1c004,
1636 .enable_reg = 0x1c004,
1637 .enable_mask = BIT(0),
1651 .halt_reg = 0x1e004,
1654 .enable_reg = 0x1e004,
1655 .enable_mask = BIT(0),
1669 .halt_reg = 0x25004,
1672 .enable_reg = 0x52004,
1682 .halt_reg = 0x26008,
1685 .enable_reg = 0x26008,
1686 .enable_mask = BIT(0),
1700 .halt_reg = 0x26004,
1703 .enable_reg = 0x26004,
1704 .enable_mask = BIT(0),
1718 .halt_reg = 0x28008,
1721 .enable_reg = 0x28008,
1722 .enable_mask = BIT(0),
1736 .halt_reg = 0x28004,
1739 .enable_reg = 0x28004,
1740 .enable_mask = BIT(0),
1754 .halt_reg = 0x2a008,
1757 .enable_reg = 0x2a008,
1758 .enable_mask = BIT(0),
1772 .halt_reg = 0x2a004,
1775 .enable_reg = 0x2a004,
1776 .enable_mask = BIT(0),
1790 .halt_reg = 0x2c008,
1793 .enable_reg = 0x2c008,
1794 .enable_mask = BIT(0),
1808 .halt_reg = 0x2c004,
1811 .enable_reg = 0x2c004,
1812 .enable_mask = BIT(0),
1826 .halt_reg = 0x2e008,
1829 .enable_reg = 0x2e008,
1830 .enable_mask = BIT(0),
1844 .halt_reg = 0x2e004,
1847 .enable_reg = 0x2e004,
1848 .enable_mask = BIT(0),
1862 .halt_reg = 0x30008,
1865 .enable_reg = 0x30008,
1866 .enable_mask = BIT(0),
1880 .halt_reg = 0x30004,
1883 .enable_reg = 0x30004,
1884 .enable_mask = BIT(0),
1898 .halt_reg = 0x25008,
1901 .enable_reg = 0x52004,
1911 .halt_reg = 0x27004,
1914 .enable_reg = 0x27004,
1915 .enable_mask = BIT(0),
1929 .halt_reg = 0x29004,
1932 .enable_reg = 0x29004,
1933 .enable_mask = BIT(0),
1947 .halt_reg = 0x2b004,
1950 .enable_reg = 0x2b004,
1951 .enable_mask = BIT(0),
1965 .halt_reg = 0x5018,
1968 .enable_reg = 0x5018,
1969 .enable_mask = BIT(0),
1983 .halt_reg = 0x64000,
1986 .enable_reg = 0x64000,
1987 .enable_mask = BIT(0),
2001 .halt_reg = 0x65000,
2004 .enable_reg = 0x65000,
2005 .enable_mask = BIT(0),
2019 .halt_reg = 0x66000,
2022 .enable_reg = 0x66000,
2023 .enable_mask = BIT(0),
2037 .halt_reg = 0x46040,
2040 .enable_reg = 0x46040,
2041 .enable_mask = BIT(0),
2050 .halt_reg = 0x71010,
2053 .enable_reg = 0x71010,
2054 .enable_mask = BIT(0),
2063 .halt_reg = 0x7100c,
2066 .enable_reg = 0x7100c,
2067 .enable_mask = BIT(0),
2076 .halt_reg = 0x71004,
2079 .enable_reg = 0x71004,
2080 .enable_mask = BIT(0),
2095 .halt_reg = 0x71018,
2098 .enable_reg = 0x71018,
2099 .enable_mask = BIT(0),
2108 .halt_reg = 0x48000,
2111 .enable_reg = 0x52004,
2126 .halt_reg = 0x48010,
2129 .enable_reg = 0x48010,
2130 .enable_mask = BIT(0),
2139 .halt_reg = 0x48008,
2142 .enable_reg = 0x48008,
2143 .enable_mask = BIT(0),
2157 .halt_reg = 0x4800c,
2160 .enable_reg = 0x4800c,
2161 .enable_mask = BIT(0),
2170 F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
2171 F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
2176 .cmd_rcgr = 0x4805c,
2189 .halt_reg = 0x9004,
2192 .enable_reg = 0x9004,
2193 .enable_mask = BIT(0),
2208 .halt_reg = 0x9030,
2211 .enable_reg = 0x9030,
2212 .enable_mask = BIT(0),
2221 .halt_reg = 0x900c,
2224 .enable_reg = 0x900c,
2225 .enable_mask = BIT(0),
2234 .halt_reg = 0x9000,
2237 .enable_reg = 0x9000,
2238 .enable_mask = BIT(0),
2247 .halt_reg = 0x8a00c,
2250 .enable_reg = 0x8a00c,
2251 .enable_mask = BIT(0),
2260 .halt_reg = 0x6b014,
2263 .enable_reg = 0x6b014,
2264 .enable_mask = BIT(0),
2278 .halt_reg = 0x6b010,
2281 .enable_reg = 0x6b010,
2282 .enable_mask = BIT(0),
2291 .halt_reg = 0x6b00c,
2294 .enable_reg = 0x6b00c,
2295 .enable_mask = BIT(0),
2304 .halt_reg = 0x6b018,
2307 .enable_reg = 0x6b018,
2308 .enable_mask = BIT(0),
2317 .halt_reg = 0x6b008,
2320 .enable_reg = 0x6b008,
2321 .enable_mask = BIT(0),
2330 .halt_reg = 0x6f004,
2333 .enable_reg = 0x6f004,
2334 .enable_mask = BIT(0),
2348 .halt_reg = 0x3300c,
2351 .enable_reg = 0x3300c,
2352 .enable_mask = BIT(0),
2366 .halt_reg = 0x33004,
2369 .enable_reg = 0x33004,
2370 .enable_mask = BIT(0),
2379 .halt_reg = 0x33008,
2382 .enable_reg = 0x33008,
2383 .enable_mask = BIT(0),
2392 .halt_reg = 0x34004,
2395 .enable_reg = 0x52004,
2405 .halt_reg = 0x14008,
2408 .enable_reg = 0x14008,
2409 .enable_mask = BIT(0),
2418 .halt_reg = 0x14004,
2421 .enable_reg = 0x14004,
2422 .enable_mask = BIT(0),
2436 .halt_reg = 0x16008,
2439 .enable_reg = 0x16008,
2440 .enable_mask = BIT(0),
2449 .halt_reg = 0x16004,
2452 .enable_reg = 0x16004,
2453 .enable_mask = BIT(0),
2467 .halt_reg = 0x36004,
2470 .enable_reg = 0x36004,
2471 .enable_mask = BIT(0),
2480 .halt_reg = 0x3600c,
2483 .enable_reg = 0x3600c,
2484 .enable_mask = BIT(0),
2493 .halt_reg = 0x36008,
2496 .enable_reg = 0x36008,
2497 .enable_mask = BIT(0),
2511 .halt_reg = 0x7500c,
2514 .enable_reg = 0x7500c,
2515 .enable_mask = BIT(0),
2524 .halt_reg = 0x75008,
2527 .enable_reg = 0x75008,
2528 .enable_mask = BIT(0),
2542 .halt_reg = 0x7600c,
2545 .enable_reg = 0x7600c,
2546 .enable_mask = BIT(0),
2555 .halt_reg = 0x76040,
2558 .enable_reg = 0x76040,
2559 .enable_mask = BIT(0),
2568 .halt_reg = 0x75014,
2571 .enable_reg = 0x75014,
2572 .enable_mask = BIT(0),
2581 .halt_reg = 0x7605c,
2584 .enable_reg = 0x7605c,
2585 .enable_mask = BIT(0),
2594 .halt_reg = 0x75010,
2597 .enable_reg = 0x75010,
2598 .enable_mask = BIT(0),
2607 .halt_reg = 0x76008,
2610 .enable_reg = 0x76008,
2611 .enable_mask = BIT(0),
2625 .halt_reg = 0xf008,
2628 .enable_reg = 0xf008,
2629 .enable_mask = BIT(0),
2643 .halt_reg = 0xf010,
2646 .enable_reg = 0xf010,
2647 .enable_mask = BIT(0),
2661 .halt_reg = 0xf00c,
2664 .enable_reg = 0xf00c,
2665 .enable_mask = BIT(0),
2674 .halt_reg = 0x50000,
2677 .enable_reg = 0x50000,
2678 .enable_mask = BIT(0),
2692 .halt_reg = 0x50004,
2695 .enable_reg = 0x50004,
2696 .enable_mask = BIT(0),
2705 .halt_reg = 0x6a004,
2708 .enable_reg = 0x6a004,
2709 .enable_mask = BIT(0),
2718 .halt_reg = 0x88000,
2720 .enable_reg = 0x88000,
2721 .enable_mask = BIT(0),
2732 .halt_reg = 0x88004,
2734 .enable_reg = 0x88004,
2735 .enable_mask = BIT(0),
2746 .halt_reg = 0x88008,
2748 .enable_reg = 0x88008,
2749 .enable_mask = BIT(0),
2760 .halt_reg = 0x8800c,
2762 .enable_reg = 0x8800c,
2763 .enable_mask = BIT(0),
2774 .halt_reg = 0x88014,
2776 .enable_reg = 0x88014,
2777 .enable_mask = BIT(0),
2788 .gdscr = 0x6b004,
2789 .gds_hw_ctrl = 0x0,
2798 .gdscr = 0x75004,
2799 .gds_hw_ctrl = 0x0,
2808 .gdscr = 0xf004,
2809 .gds_hw_ctrl = 0x0,
2999 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3000 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3001 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3002 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3003 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3004 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3005 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3006 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3007 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3008 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3009 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3010 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3011 [GCC_PCIE_0_BCR] = { 0x6b000 },
3012 [GCC_PDM_BCR] = { 0x33000 },
3013 [GCC_SDCC2_BCR] = { 0x14000 },
3014 [GCC_SDCC4_BCR] = { 0x16000 },
3015 [GCC_TSIF_BCR] = { 0x36000 },
3016 [GCC_UFS_BCR] = { 0x75000 },
3017 [GCC_USB_30_BCR] = { 0xf000 },
3018 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3019 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3020 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
3021 [GCC_IMEM_BCR] = { 0x8000 },
3022 [GCC_PIMEM_BCR] = { 0xa000 },
3023 [GCC_MMSS_BCR] = { 0xb000 },
3024 [GCC_QDSS_BCR] = { 0xc000 },
3025 [GCC_WCSS_BCR] = { 0x11000 },
3026 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3027 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3028 [GCC_BLSP1_BCR] = { 0x17000 },
3029 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3030 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3031 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3032 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
3033 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
3034 [GCC_BLSP2_BCR] = { 0x25000 },
3035 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3036 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3037 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3038 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
3039 [GCC_PRNG_BCR] = { 0x34000 },
3040 [GCC_TSIF_0_RESET] = { 0x36024 },
3041 [GCC_TSIF_1_RESET] = { 0x36028 },
3042 [GCC_TCSR_BCR] = { 0x37000 },
3043 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3044 [GCC_MSG_RAM_BCR] = { 0x39000 },
3045 [GCC_TLMM_BCR] = { 0x3a000 },
3046 [GCC_MPM_BCR] = { 0x3b000 },
3047 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3048 [GCC_SPMI_BCR] = { 0x3f000 },
3049 [GCC_SPDM_BCR] = { 0x40000 },
3050 [GCC_CE1_BCR] = { 0x41000 },
3051 [GCC_BIMC_BCR] = { 0x44000 },
3052 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3053 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
3054 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
3055 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
3056 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3057 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
3058 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
3059 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3060 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3061 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3062 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3063 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3064 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3065 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3066 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3067 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3068 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3069 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3070 [GCC_USB3_PHY_BCR] = { 0x50020 },
3071 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3072 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
3073 [GCC_SSC_BCR] = { 0x63000 },
3074 [GCC_SSC_RESET] = { 0x63020 },
3075 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3076 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3077 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3078 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3079 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3080 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
3081 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
3082 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3083 [GCC_GPU_BCR] = { 0x71000 },
3084 [GCC_SPSS_BCR] = { 0x72000 },
3085 [GCC_OBT_ODT_BCR] = { 0x73000 },
3086 [GCC_MSS_RESTART] = { 0x79000 },
3087 [GCC_VS_BCR] = { 0x7a000 },
3088 [GCC_MSS_VS_RESET] = { 0x7a100 },
3089 [GCC_GPU_VS_RESET] = { 0x7a104 },
3090 [GCC_APC0_VS_RESET] = { 0x7a108 },
3091 [GCC_APC1_VS_RESET] = { 0x7a10c },
3092 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3093 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3094 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
3095 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
3096 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
3097 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
3098 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
3099 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
3100 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3101 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3102 [GCC_DCC_BCR] = { 0x84000 },
3103 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
3104 [GCC_IPA_BCR] = { 0x89000 },
3105 [GCC_GLM_BCR] = { 0x8b000 },
3106 [GCC_SKL_BCR] = { 0x8c000 },
3107 [GCC_MSMPU_BCR] = { 0x8d000 },
3114 .max_register = 0x8f000,
3147 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_msm8998_probe()