Lines Matching +full:0 +full:x1740
36 { P_XO, 0 },
46 { P_XO, 0 },
58 .l_reg = 0x0004,
59 .m_reg = 0x0008,
60 .n_reg = 0x000c,
61 .config_reg = 0x0014,
62 .mode_reg = 0x0000,
63 .status_reg = 0x001c,
74 .enable_reg = 0x1480,
75 .enable_mask = BIT(0),
85 .cmd_rcgr = 0x0150,
97 .cmd_rcgr = 0x0190,
109 .cmd_rcgr = 0x0120,
121 .l_reg = 0x0044,
122 .m_reg = 0x0048,
123 .n_reg = 0x004c,
124 .config_reg = 0x0054,
125 .mode_reg = 0x0040,
126 .status_reg = 0x005c,
137 .enable_reg = 0x1480,
148 .l_reg = 0x1dc4,
149 .m_reg = 0x1dc8,
150 .n_reg = 0x1dcc,
151 .config_reg = 0x1dd4,
152 .mode_reg = 0x1dc0,
153 .status_reg = 0x1ddc,
164 .enable_reg = 0x1480,
180 .cmd_rcgr = 0x03d4,
194 F(19200000, P_XO, 1, 0, 0),
195 F(37500000, P_GPLL0, 16, 0, 0),
196 F(50000000, P_GPLL0, 12, 0, 0),
201 .cmd_rcgr = 0x0660,
215 F(4800000, P_XO, 4, 0, 0),
216 F(9600000, P_XO, 2, 0, 0),
218 F(19200000, P_XO, 1, 0, 0),
220 F(50000000, P_GPLL0, 12, 0, 0),
225 .cmd_rcgr = 0x064c,
239 .cmd_rcgr = 0x06e0,
252 .cmd_rcgr = 0x06cc,
266 .cmd_rcgr = 0x0760,
279 .cmd_rcgr = 0x074c,
293 .cmd_rcgr = 0x07e0,
306 .cmd_rcgr = 0x07cc,
320 .cmd_rcgr = 0x0860,
333 .cmd_rcgr = 0x084c,
347 .cmd_rcgr = 0x08e0,
360 .cmd_rcgr = 0x08cc,
378 F(19200000, P_XO, 1, 0, 0),
381 F(40000000, P_GPLL0, 15, 0, 0),
383 F(48000000, P_GPLL0, 12.5, 0, 0),
387 F(60000000, P_GPLL0, 10, 0, 0),
388 F(63160000, P_GPLL0, 9.5, 0, 0),
393 .cmd_rcgr = 0x068c,
407 .cmd_rcgr = 0x070c,
421 .cmd_rcgr = 0x078c,
435 .cmd_rcgr = 0x080c,
449 .cmd_rcgr = 0x088c,
463 .cmd_rcgr = 0x090c,
477 .cmd_rcgr = 0x09a0,
490 .cmd_rcgr = 0x098c,
504 .cmd_rcgr = 0x0a20,
517 .cmd_rcgr = 0x0a0c,
531 .cmd_rcgr = 0x0aa0,
544 .cmd_rcgr = 0x0a8c,
558 .cmd_rcgr = 0x0b20,
571 .cmd_rcgr = 0x0b0c,
585 .cmd_rcgr = 0x0ba0,
598 .cmd_rcgr = 0x0b8c,
612 .cmd_rcgr = 0x0c20,
625 .cmd_rcgr = 0x0c0c,
639 .cmd_rcgr = 0x09cc,
653 .cmd_rcgr = 0x0a4c,
667 .cmd_rcgr = 0x0acc,
681 .cmd_rcgr = 0x0b4c,
695 .cmd_rcgr = 0x0bcc,
709 .cmd_rcgr = 0x0c4c,
723 F(50000000, P_GPLL0, 12, 0, 0),
724 F(100000000, P_GPLL0, 6, 0, 0),
729 F(50000000, P_GPLL0, 12, 0, 0),
730 F(75000000, P_GPLL0, 8, 0, 0),
731 F(100000000, P_GPLL0, 6, 0, 0),
732 F(150000000, P_GPLL0, 4, 0, 0),
737 .cmd_rcgr = 0x1050,
750 F(50000000, P_GPLL0, 12, 0, 0),
751 F(75000000, P_GPLL0, 8, 0, 0),
752 F(100000000, P_GPLL0, 6, 0, 0),
753 F(150000000, P_GPLL0, 4, 0, 0),
758 .cmd_rcgr = 0x1090,
771 F(19200000, P_XO, 1, 0, 0),
776 F(4800000, P_XO, 4, 0, 0),
780 F(9600000, P_XO, 2, 0, 0),
782 F(19200000, P_XO, 1, 0, 0),
789 .cmd_rcgr = 0x1904,
803 .cmd_rcgr = 0x1944,
817 .cmd_rcgr = 0x1984,
831 F(60000000, P_GPLL0, 10, 0, 0),
836 .cmd_rcgr = 0x0cd0,
853 F(50000000, P_GPLL0, 12, 0, 0),
854 F(100000000, P_GPLL0, 6, 0, 0),
855 F(200000000, P_GPLL0, 3, 0, 0),
864 F(50000000, P_GPLL0, 12, 0, 0),
865 F(100000000, P_GPLL0, 6, 0, 0),
866 F(192000000, P_GPLL4, 4, 0, 0),
867 F(200000000, P_GPLL0, 3, 0, 0),
868 F(384000000, P_GPLL4, 2, 0, 0),
880 .cmd_rcgr = 0x04d0,
889 .cmd_rcgr = 0x0510,
903 .cmd_rcgr = 0x0550,
917 .cmd_rcgr = 0x0590,
936 .cmd_rcgr = 0x0d90,
950 F(60000000, P_GPLL0, 10, 0, 0),
955 .cmd_rcgr = 0x03e8,
968 F(60000000, P_GPLL0, 10, 0, 0),
969 F(75000000, P_GPLL0, 8, 0, 0),
974 .cmd_rcgr = 0x0490,
987 F(480000000, P_GPLL1, 1, 0, 0),
992 { P_XO, 0 },
997 .cmd_rcgr = 0x0440,
1013 F(9600000, P_XO, 2, 0, 0),
1018 .cmd_rcgr = 0x0458,
1031 F(60000000, P_GPLL0, 10, 0, 0),
1032 F(75000000, P_GPLL0, 8, 0, 0),
1037 .cmd_rcgr = 0x041c,
1050 .enable_reg = 0x1484,
1063 .halt_reg = 0x0d44,
1066 .enable_reg = 0x1484,
1080 .halt_reg = 0x05c4,
1083 .enable_reg = 0x1484,
1097 .halt_reg = 0x0648,
1099 .enable_reg = 0x0648,
1100 .enable_mask = BIT(0),
1114 .halt_reg = 0x0644,
1116 .enable_reg = 0x0644,
1117 .enable_mask = BIT(0),
1131 .halt_reg = 0x06c8,
1133 .enable_reg = 0x06c8,
1134 .enable_mask = BIT(0),
1148 .halt_reg = 0x06c4,
1150 .enable_reg = 0x06c4,
1151 .enable_mask = BIT(0),
1165 .halt_reg = 0x0748,
1167 .enable_reg = 0x0748,
1168 .enable_mask = BIT(0),
1182 .halt_reg = 0x0744,
1184 .enable_reg = 0x0744,
1185 .enable_mask = BIT(0),
1199 .halt_reg = 0x07c8,
1201 .enable_reg = 0x07c8,
1202 .enable_mask = BIT(0),
1216 .halt_reg = 0x07c4,
1218 .enable_reg = 0x07c4,
1219 .enable_mask = BIT(0),
1233 .halt_reg = 0x0848,
1235 .enable_reg = 0x0848,
1236 .enable_mask = BIT(0),
1250 .halt_reg = 0x0844,
1252 .enable_reg = 0x0844,
1253 .enable_mask = BIT(0),
1267 .halt_reg = 0x08c8,
1269 .enable_reg = 0x08c8,
1270 .enable_mask = BIT(0),
1284 .halt_reg = 0x08c4,
1286 .enable_reg = 0x08c4,
1287 .enable_mask = BIT(0),
1301 .halt_reg = 0x0684,
1303 .enable_reg = 0x0684,
1304 .enable_mask = BIT(0),
1318 .halt_reg = 0x0704,
1320 .enable_reg = 0x0704,
1321 .enable_mask = BIT(0),
1335 .halt_reg = 0x0784,
1337 .enable_reg = 0x0784,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0x0804,
1354 .enable_reg = 0x0804,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x0884,
1371 .enable_reg = 0x0884,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x0904,
1388 .enable_reg = 0x0904,
1389 .enable_mask = BIT(0),
1403 .halt_reg = 0x0944,
1406 .enable_reg = 0x1484,
1420 .halt_reg = 0x0988,
1422 .enable_reg = 0x0988,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x0984,
1439 .enable_reg = 0x0984,
1440 .enable_mask = BIT(0),
1454 .halt_reg = 0x0a08,
1456 .enable_reg = 0x0a08,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0x0a04,
1473 .enable_reg = 0x0a04,
1474 .enable_mask = BIT(0),
1488 .halt_reg = 0x0a88,
1490 .enable_reg = 0x0a88,
1491 .enable_mask = BIT(0),
1505 .halt_reg = 0x0a84,
1507 .enable_reg = 0x0a84,
1508 .enable_mask = BIT(0),
1522 .halt_reg = 0x0b08,
1524 .enable_reg = 0x0b08,
1525 .enable_mask = BIT(0),
1539 .halt_reg = 0x0b04,
1541 .enable_reg = 0x0b04,
1542 .enable_mask = BIT(0),
1556 .halt_reg = 0x0b88,
1558 .enable_reg = 0x0b88,
1559 .enable_mask = BIT(0),
1573 .halt_reg = 0x0b84,
1575 .enable_reg = 0x0b84,
1576 .enable_mask = BIT(0),
1590 .halt_reg = 0x0c08,
1592 .enable_reg = 0x0c08,
1593 .enable_mask = BIT(0),
1607 .halt_reg = 0x0c04,
1609 .enable_reg = 0x0c04,
1610 .enable_mask = BIT(0),
1624 .halt_reg = 0x09c4,
1626 .enable_reg = 0x09c4,
1627 .enable_mask = BIT(0),
1641 .halt_reg = 0x0a44,
1643 .enable_reg = 0x0a44,
1644 .enable_mask = BIT(0),
1658 .halt_reg = 0x0ac4,
1660 .enable_reg = 0x0ac4,
1661 .enable_mask = BIT(0),
1675 .halt_reg = 0x0b44,
1677 .enable_reg = 0x0b44,
1678 .enable_mask = BIT(0),
1692 .halt_reg = 0x0bc4,
1694 .enable_reg = 0x0bc4,
1695 .enable_mask = BIT(0),
1709 .halt_reg = 0x0c44,
1711 .enable_reg = 0x0c44,
1712 .enable_mask = BIT(0),
1726 .halt_reg = 0x0e04,
1729 .enable_reg = 0x1484,
1743 .halt_reg = 0x104c,
1746 .enable_reg = 0x1484,
1760 .halt_reg = 0x1048,
1763 .enable_reg = 0x1484,
1777 .halt_reg = 0x1050,
1780 .enable_reg = 0x1484,
1795 .halt_reg = 0x108c,
1798 .enable_reg = 0x1484,
1799 .enable_mask = BIT(0),
1812 .halt_reg = 0x1088,
1815 .enable_reg = 0x1484,
1829 .halt_reg = 0x1090,
1832 .enable_reg = 0x1484,
1847 .halt_reg = 0x1900,
1849 .enable_reg = 0x1900,
1850 .enable_mask = BIT(0),
1864 .halt_reg = 0x1940,
1866 .enable_reg = 0x1940,
1867 .enable_mask = BIT(0),
1881 .halt_reg = 0x1980,
1883 .enable_reg = 0x1980,
1884 .enable_mask = BIT(0),
1898 .halt_reg = 0x11c0,
1900 .enable_reg = 0x11c0,
1901 .enable_mask = BIT(0),
1914 .halt_reg = 0x024c,
1916 .enable_reg = 0x024c,
1917 .enable_mask = BIT(0),
1931 .halt_reg = 0x0248,
1933 .enable_reg = 0x0248,
1934 .enable_mask = BIT(0),
1947 .halt_reg = 0x0280,
1949 .enable_reg = 0x0280,
1950 .enable_mask = BIT(0),
1963 .halt_reg = 0x0284,
1965 .enable_reg = 0x0284,
1966 .enable_mask = BIT(0),
1979 .halt_reg = 0x0ccc,
1981 .enable_reg = 0x0ccc,
1982 .enable_mask = BIT(0),
1996 .halt_reg = 0x0cc4,
1998 .enable_reg = 0x0cc4,
1999 .enable_mask = BIT(0),
2012 .halt_reg = 0x0cc8,
2014 .enable_reg = 0x0cc8,
2015 .enable_mask = BIT(0),
2026 .halt_reg = 0x0d04,
2029 .enable_reg = 0x1484,
2043 .halt_reg = 0x04c8,
2045 .enable_reg = 0x04c8,
2046 .enable_mask = BIT(0),
2059 .halt_reg = 0x04c4,
2061 .enable_reg = 0x04c4,
2062 .enable_mask = BIT(0),
2076 .halt_reg = 0x04e8,
2078 .enable_reg = 0x04e8,
2079 .enable_mask = BIT(0),
2092 .halt_reg = 0x04e4,
2094 .enable_reg = 0x04e4,
2095 .enable_mask = BIT(0),
2108 .halt_reg = 0x0508,
2110 .enable_reg = 0x0508,
2111 .enable_mask = BIT(0),
2124 .halt_reg = 0x0504,
2126 .enable_reg = 0x0504,
2127 .enable_mask = BIT(0),
2141 .halt_reg = 0x0548,
2143 .enable_reg = 0x0548,
2144 .enable_mask = BIT(0),
2157 .halt_reg = 0x0544,
2159 .enable_reg = 0x0544,
2160 .enable_mask = BIT(0),
2174 .halt_reg = 0x0588,
2176 .enable_reg = 0x0588,
2177 .enable_mask = BIT(0),
2190 .halt_reg = 0x0584,
2192 .enable_reg = 0x0584,
2193 .enable_mask = BIT(0),
2207 .halt_reg = 0x0108,
2209 .enable_reg = 0x0108,
2210 .enable_mask = BIT(0),
2224 .halt_reg = 0x0d84,
2226 .enable_reg = 0x0d84,
2227 .enable_mask = BIT(0),
2240 .halt_reg = 0x0d88,
2242 .enable_reg = 0x0d88,
2243 .enable_mask = BIT(0),
2257 .halt_reg = 0x04ac,
2259 .enable_reg = 0x04ac,
2260 .enable_mask = BIT(0),
2273 .halt_reg = 0x04b4,
2275 .enable_reg = 0x04b4,
2276 .enable_mask = BIT(0),
2289 .halt_reg = 0x03c8,
2291 .enable_reg = 0x03c8,
2292 .enable_mask = BIT(0),
2306 .halt_reg = 0x03d0,
2308 .enable_reg = 0x03d0,
2309 .enable_mask = BIT(0),
2323 .halt_reg = 0x03cc,
2325 .enable_reg = 0x03cc,
2326 .enable_mask = BIT(0),
2339 .halt_reg = 0x0488,
2341 .enable_reg = 0x0488,
2342 .enable_mask = BIT(0),
2355 .halt_reg = 0x0484,
2357 .enable_reg = 0x0484,
2358 .enable_mask = BIT(0),
2372 .halt_reg = 0x0408,
2374 .enable_reg = 0x0408,
2375 .enable_mask = BIT(0),
2388 .halt_reg = 0x0410,
2390 .enable_reg = 0x0410,
2391 .enable_mask = BIT(0),
2405 .halt_reg = 0x0414,
2407 .enable_reg = 0x0414,
2408 .enable_mask = BIT(0),
2422 .halt_reg = 0x0418,
2424 .enable_reg = 0x0418,
2425 .enable_mask = BIT(0),
2438 .halt_reg = 0x040c,
2440 .enable_reg = 0x040c,
2441 .enable_mask = BIT(0),
2455 .gdscr = 0x404,
2550 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2551 [GCC_USB_HS_BCR] = { 0x0480 },
2552 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2563 .max_register = 0x1a80,
2726 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2727 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2728 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2729 [GCC_IMEM_BCR] = { 0x0200 },
2730 [GCC_MMSS_BCR] = { 0x0240 },
2731 [GCC_QDSS_BCR] = { 0x0300 },
2732 [GCC_USB_30_BCR] = { 0x03c0 },
2733 [GCC_USB3_PHY_BCR] = { 0x03fc },
2734 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2735 [GCC_USB_HS_BCR] = { 0x0480 },
2736 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2737 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2738 [GCC_SDCC1_BCR] = { 0x04c0 },
2739 [GCC_SDCC2_BCR] = { 0x0500 },
2740 [GCC_SDCC3_BCR] = { 0x0540 },
2741 [GCC_SDCC4_BCR] = { 0x0580 },
2742 [GCC_BLSP1_BCR] = { 0x05c0 },
2743 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2744 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2745 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2746 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2747 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2748 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2749 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2750 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2751 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2752 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2753 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2754 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2755 [GCC_BLSP2_BCR] = { 0x0940 },
2756 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2757 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2758 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2759 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2760 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2761 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2762 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2763 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2764 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2765 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2766 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2767 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2768 [GCC_PDM_BCR] = { 0x0cc0 },
2769 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2770 [GCC_TSIF_BCR] = { 0x0d80 },
2771 [GCC_TCSR_BCR] = { 0x0dc0 },
2772 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2773 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2774 [GCC_TLMM_BCR] = { 0x0e80 },
2775 [GCC_MPM_BCR] = { 0x0ec0 },
2776 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2777 [GCC_SPMI_BCR] = { 0x0fc0 },
2778 [GCC_SPDM_BCR] = { 0x1000 },
2779 [GCC_CE1_BCR] = { 0x1040 },
2780 [GCC_CE2_BCR] = { 0x1080 },
2781 [GCC_BIMC_BCR] = { 0x1100 },
2782 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2783 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2784 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2785 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2786 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2787 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2788 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2789 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2790 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2791 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2792 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2793 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2794 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2795 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2796 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2797 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2798 [GCC_DEHR_BCR] = { 0x1300 },
2799 [GCC_RBCPR_BCR] = { 0x1380 },
2800 [GCC_MSS_RESTART] = { 0x1680 },
2801 [GCC_LPASS_RESTART] = { 0x16c0 },
2802 [GCC_WCSS_RESTART] = { 0x1700 },
2803 [GCC_VENUS_RESTART] = { 0x1740 },
2814 .max_register = 0x1fc0,