Lines Matching +full:0 +full:x3d00
29 .l_reg = 0x30c4,
30 .m_reg = 0x30c8,
31 .n_reg = 0x30cc,
32 .config_reg = 0x30d4,
33 .mode_reg = 0x30c0,
34 .status_reg = 0x30d8,
45 .enable_reg = 0x34c0,
46 .enable_mask = BIT(0),
56 .l_reg = 0x3164,
57 .m_reg = 0x3168,
58 .n_reg = 0x316c,
59 .config_reg = 0x3174,
60 .mode_reg = 0x3160,
61 .status_reg = 0x3178,
72 .enable_reg = 0x34c0,
83 .l_reg = 0x3144,
84 .m_reg = 0x3148,
85 .n_reg = 0x314c,
86 .config_reg = 0x3154,
87 .mode_reg = 0x3140,
88 .status_reg = 0x3158,
99 .enable_reg = 0x34c0,
110 .mode_reg = 0x3200,
111 .l_reg = 0x3208,
112 .m_reg = 0x320c,
113 .n_reg = 0x3210,
114 .config_reg = 0x3204,
115 .status_reg = 0x321c,
116 .config_val = 0x7845c665,
117 .droop_reg = 0x3214,
118 .droop_val = 0x0108c000,
136 .mode_reg = 0x3240,
137 .l_reg = 0x3248,
138 .m_reg = 0x324c,
139 .n_reg = 0x3250,
140 .config_reg = 0x3244,
141 .status_reg = 0x325c,
142 .config_val = 0x7845c665,
143 .droop_reg = 0x3314,
144 .droop_val = 0x0108c000,
162 .mode_reg = 0x3300,
163 .l_reg = 0x3308,
164 .m_reg = 0x330c,
165 .n_reg = 0x3310,
166 .config_reg = 0x3304,
167 .status_reg = 0x331c,
168 .config_val = 0x7845c665,
169 .droop_reg = 0x3314,
170 .droop_val = 0x0108c000,
188 .l_reg = 0x31c4,
189 .m_reg = 0x31c8,
190 .n_reg = 0x31cc,
191 .config_reg = 0x31d4,
192 .mode_reg = 0x31c0,
193 .status_reg = 0x31d8,
204 .enable_reg = 0x34c0,
224 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
225 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
229 .l_reg = 0x31a4,
230 .m_reg = 0x31a8,
231 .n_reg = 0x31ac,
232 .config_reg = 0x31b4,
233 .mode_reg = 0x31a0,
234 .status_reg = 0x31b8,
258 { P_PXO, 0 },
268 { P_PXO, 0 },
280 { P_PXO, 0 },
285 { P_PXO, 0 },
295 { P_PXO, 0 },
307 { P_PXO, 0 },
341 .ns_reg = 0x29d4,
342 .md_reg = 0x29d0,
356 .src_sel_shift = 0,
361 .enable_reg = 0x29d4,
374 .halt_reg = 0x2fcc,
377 .enable_reg = 0x29d4,
392 .ns_reg = 0x29f4,
393 .md_reg = 0x29f0,
407 .src_sel_shift = 0,
412 .enable_reg = 0x29f4,
425 .halt_reg = 0x2fcc,
428 .enable_reg = 0x29f4,
443 .ns_reg = 0x2a34,
444 .md_reg = 0x2a30,
458 .src_sel_shift = 0,
463 .enable_reg = 0x2a34,
476 .halt_reg = 0x2fd0,
479 .enable_reg = 0x2a34,
494 .ns_reg = 0x2a54,
495 .md_reg = 0x2a50,
509 .src_sel_shift = 0,
514 .enable_reg = 0x2a54,
527 .halt_reg = 0x2fd0,
530 .enable_reg = 0x2a54,
545 .ns_reg = 0x2a74,
546 .md_reg = 0x2a70,
560 .src_sel_shift = 0,
565 .enable_reg = 0x2a74,
578 .halt_reg = 0x2fd0,
581 .enable_reg = 0x2a74,
596 .ns_reg = 0x2a94,
597 .md_reg = 0x2a90,
611 .src_sel_shift = 0,
616 .enable_reg = 0x2a94,
629 .halt_reg = 0x2fd0,
632 .enable_reg = 0x2a94,
652 { 25000000, P_PXO, 1, 0, 0 },
660 .ns_reg = 0x29cc,
661 .md_reg = 0x29c8,
675 .src_sel_shift = 0,
680 .enable_reg = 0x29cc,
693 .halt_reg = 0x2fcc,
696 .enable_reg = 0x29cc,
709 .ns_reg = 0x29ec,
710 .md_reg = 0x29e8,
724 .src_sel_shift = 0,
729 .enable_reg = 0x29ec,
742 .halt_reg = 0x2fcc,
745 .enable_reg = 0x29ec,
758 .ns_reg = 0x2a2c,
759 .md_reg = 0x2a28,
773 .src_sel_shift = 0,
778 .enable_reg = 0x2a2c,
791 .halt_reg = 0x2fd0,
794 .enable_reg = 0x2a2c,
807 .ns_reg = 0x2a4c,
808 .md_reg = 0x2a48,
822 .src_sel_shift = 0,
827 .enable_reg = 0x2a4c,
840 .halt_reg = 0x2fd0,
843 .enable_reg = 0x2a4c,
856 .ns_reg = 0x2a6c,
857 .md_reg = 0x2a68,
871 .src_sel_shift = 0,
876 .enable_reg = 0x2a6c,
889 .halt_reg = 0x2fd0,
892 .enable_reg = 0x2a6c,
905 .ns_reg = 0x2a8c,
906 .md_reg = 0x2a88,
920 .src_sel_shift = 0,
925 .enable_reg = 0x2a8c,
938 .halt_reg = 0x2fd0,
941 .enable_reg = 0x2a8c,
954 .hwcg_reg = 0x29c0,
956 .halt_reg = 0x2fcc,
959 .enable_reg = 0x29c0,
969 .hwcg_reg = 0x29e0,
971 .halt_reg = 0x2fcc,
974 .enable_reg = 0x29e0,
984 .hwcg_reg = 0x2a20,
986 .halt_reg = 0x2fd0,
989 .enable_reg = 0x2a20,
999 .hwcg_reg = 0x2a40,
1001 .halt_reg = 0x2fd0,
1004 .enable_reg = 0x2a40,
1014 .hwcg_reg = 0x2a60,
1016 .halt_reg = 0x2fd0,
1019 .enable_reg = 0x2a60,
1029 .hwcg_reg = 0x2a80,
1031 .halt_reg = 0x2fd0,
1034 .enable_reg = 0x2a80,
1044 { 12500000, P_PXO, 2, 0, 0 },
1045 { 25000000, P_PXO, 1, 0, 0 },
1048 { 96000000, P_PLL8, 4, 0, 0 },
1049 { 128000000, P_PLL8, 3, 0, 0 },
1050 { 192000000, P_PLL8, 2, 0, 0 },
1055 .ns_reg = 0x2d24,
1056 .md_reg = 0x2d00,
1070 .src_sel_shift = 0,
1075 .enable_reg = 0x2d24,
1088 .halt_reg = 0x2fd8,
1091 .enable_reg = 0x2d24,
1104 .ns_reg = 0x2d44,
1105 .md_reg = 0x2d40,
1119 .src_sel_shift = 0,
1124 .enable_reg = 0x2d44,
1137 .halt_reg = 0x2fd8,
1140 .enable_reg = 0x2d44,
1153 .ns_reg = 0x2d64,
1154 .md_reg = 0x2d60,
1168 .src_sel_shift = 0,
1173 .enable_reg = 0x2d64,
1186 .halt_reg = 0x2fd8,
1189 .enable_reg = 0x2d64,
1202 .hwcg_reg = 0x25a0,
1204 .halt_reg = 0x2fc8,
1207 .enable_reg = 0x25a0,
1217 .ns_reg = 0x2e80,
1223 .src_sel_shift = 0,
1227 .enable_reg = 0x2e80,
1239 .halt_reg = 0x2fd8,
1243 .enable_reg = 0x3080,
1263 { 96000000, P_PLL8, 4, 0, 0 },
1264 { 192000000, P_PLL8, 2, 0, 0 },
1269 .ns_reg = 0x282c,
1270 .md_reg = 0x2828,
1284 .src_sel_shift = 0,
1289 .enable_reg = 0x282c,
1301 .halt_reg = 0x2fc8,
1304 .enable_reg = 0x282c,
1317 .ns_reg = 0x286c,
1318 .md_reg = 0x2868,
1332 .src_sel_shift = 0,
1337 .enable_reg = 0x286c,
1349 .halt_reg = 0x2fc8,
1352 .enable_reg = 0x286c,
1365 .hwcg_reg = 0x2820,
1367 .halt_reg = 0x2fc8,
1370 .enable_reg = 0x2820,
1380 .hwcg_reg = 0x2860,
1382 .halt_reg = 0x2fc8,
1385 .enable_reg = 0x2860,
1400 .ns_reg = 0x2710,
1401 .md_reg = 0x270c,
1415 .src_sel_shift = 0,
1420 .enable_reg = 0x2710,
1432 .halt_reg = 0x2fd4,
1435 .enable_reg = 0x2710,
1448 .hwcg_reg = 0x2700,
1450 .halt_reg = 0x2fd4,
1453 .enable_reg = 0x2700,
1463 .hwcg_reg = 0x25c0,
1465 .halt_reg = 0x2fc8,
1468 .enable_reg = 0x25c0,
1478 .halt_reg = 0x2fdc,
1482 .enable_reg = 0x3080,
1492 .hwcg_reg = 0x2208,
1494 .halt_reg = 0x2fdc,
1498 .enable_reg = 0x3080,
1508 .halt_reg = 0x2fd8,
1512 .enable_reg = 0x3080,
1522 .halt_reg = 0x2fd8,
1526 .enable_reg = 0x3080,
1536 .halt_reg = 0x2fd8,
1540 .enable_reg = 0x3080,
1550 .hwcg_reg = 0x27e0,
1552 .halt_reg = 0x2fd8,
1556 .enable_reg = 0x3080,
1566 { 100000000, P_PLL3, 12, 0, 0 },
1571 .ns_reg = 0x3860,
1577 .src_sel_shift = 0,
1582 .enable_reg = 0x3860,
1595 .halt_reg = 0x2fdc,
1598 .enable_reg = 0x3860,
1611 .halt_reg = 0x2fc0,
1614 .enable_reg = 0x22c0,
1624 .halt_reg = 0x2fdc,
1627 .enable_reg = 0x22c8,
1637 .halt_reg = 0x2fd4,
1640 .enable_reg = 0x22cc,
1650 .halt_reg = 0x2fdc,
1653 .enable_reg = 0x22d0,
1663 .ns_reg = 0x3aa0,
1669 .src_sel_shift = 0,
1674 .enable_reg = 0x3aa0,
1687 .halt_reg = 0x2fdc,
1690 .enable_reg = 0x3aa0,
1703 .halt_reg = 0x2fc0,
1706 .enable_reg = 0x3a80,
1716 .halt_reg = 0x2fdc,
1719 .enable_reg = 0x3a88,
1729 .halt_reg = 0x2fd4,
1732 .enable_reg = 0x3a8c,
1742 .halt_reg = 0x2fdc,
1745 .enable_reg = 0x3a90,
1755 .ns_reg = 0x3ae0,
1761 .src_sel_shift = 0,
1766 .enable_reg = 0x3ae0,
1779 .halt_reg = 0x2fdc,
1782 .enable_reg = 0x3ae0,
1795 .halt_reg = 0x2fc0,
1798 .enable_reg = 0x3ac0,
1808 .halt_reg = 0x2fdc,
1811 .enable_reg = 0x3ac8,
1821 .halt_reg = 0x2fd4,
1824 .enable_reg = 0x3acc,
1834 .halt_reg = 0x2fdc,
1837 .enable_reg = 0x3ad0,
1847 { 100000000, P_PLL3, 12, 0, 0 },
1852 .ns_reg = 0x2c08,
1858 .src_sel_shift = 0,
1863 .enable_reg = 0x2c08,
1876 .halt_reg = 0x2fdc,
1879 .enable_reg = 0x2c0c,
1892 .halt_reg = 0x2fdc,
1895 .enable_reg = 0x2c10,
1908 .halt_reg = 0x2fdc,
1911 .enable_reg = 0x2c14,
1923 .halt_reg = 0x2fc0,
1926 .enable_reg = 0x2c20,
1936 .halt_reg = 0x2fdc,
1939 .enable_reg = 0x2c00,
1949 .halt_reg = 0x2fc4,
1952 .enable_reg = 0x2480,
1962 .halt_reg = 0x2fcc,
1965 .enable_reg = 0x2c40,
1980 .ns_reg = 0x3b2c,
1981 .md_reg = 0x3b28,
1995 .src_sel_shift = 0,
2000 .enable_reg = 0x3b2c,
2013 .halt_reg = 0x2fc4,
2016 .enable_reg = 0x3b24,
2029 .halt_reg = 0x2fc4,
2032 .enable_reg = 0x3b34,
2050 .ns_reg = 0x3b44,
2051 .md_reg = 0x3b40,
2065 .src_sel_shift = 0,
2070 .enable_reg = 0x3b44,
2083 .halt_reg = 0x2fc4,
2086 .enable_reg = 0x3b48,
2099 .halt_reg = 0x2fc4,
2102 .enable_reg = 0x3b4c,
2120 .ns_reg = 0x290C,
2121 .md_reg = 0x2908,
2135 .src_sel_shift = 0,
2140 .enable_reg = 0x2968,
2153 .halt_reg = 0x2fcc,
2156 .enable_reg = 0x290c,
2169 .hwcg_reg = 0x2900,
2171 .halt_reg = 0x2fc8,
2174 .enable_reg = 0x2900,
2184 .ns_reg = 0x2968,
2185 .md_reg = 0x2964,
2199 .src_sel_shift = 0,
2204 .enable_reg = 0x2968,
2217 .halt_reg = 0x2fcc,
2220 .enable_reg = 0x2968,
2233 .halt_reg = 0x2fcc,
2236 .enable_reg = 0x296c,
2249 .halt_reg = 0x2fcc,
2252 .enable_reg = 0x2960,
2262 .hwcg_reg = 0x3b00,
2264 .halt_reg = 0x2fcc,
2267 .enable_reg = 0x3b00,
2277 .halt_reg = 0x2fcc,
2278 .halt_bit = 0,
2280 .enable_reg = 0x3b00,
2296 .ns_reg[0] = 0x3cac,
2297 .ns_reg[1] = 0x3cb0,
2298 .md_reg[0] = 0x3ca4,
2299 .md_reg[1] = 0x3ca8,
2300 .bank_reg = 0x3ca0,
2301 .mn[0] = {
2317 .s[0] = {
2318 .src_sel_shift = 0,
2322 .src_sel_shift = 0,
2325 .p[0] = {
2333 .mux_sel_bit = 0,
2336 .enable_reg = 0x3ca0,
2348 .halt_reg = 0x3c20,
2350 .hwcg_reg = 0x3cb4,
2353 .enable_reg = 0x3cb4,
2368 .ns_reg[0] = 0x3ccc,
2369 .ns_reg[1] = 0x3cd0,
2370 .md_reg[0] = 0x3cc4,
2371 .md_reg[1] = 0x3cc8,
2372 .bank_reg = 0x3ca0,
2373 .mn[0] = {
2389 .s[0] = {
2390 .src_sel_shift = 0,
2394 .src_sel_shift = 0,
2397 .p[0] = {
2405 .mux_sel_bit = 0,
2408 .enable_reg = 0x3cc0,
2420 .halt_reg = 0x3c20,
2422 .hwcg_reg = 0x3cd4,
2425 .enable_reg = 0x3cd4,
2440 .ns_reg[0] = 0x3cec,
2441 .ns_reg[1] = 0x3cf0,
2442 .md_reg[0] = 0x3ce4,
2443 .md_reg[1] = 0x3ce8,
2444 .bank_reg = 0x3ce0,
2445 .mn[0] = {
2461 .s[0] = {
2462 .src_sel_shift = 0,
2466 .src_sel_shift = 0,
2469 .p[0] = {
2477 .mux_sel_bit = 0,
2480 .enable_reg = 0x3ce0,
2492 .halt_reg = 0x3c20,
2494 .hwcg_reg = 0x3cf4,
2497 .enable_reg = 0x3cf4,
2512 .ns_reg[0] = 0x3d0c,
2513 .ns_reg[1] = 0x3d10,
2514 .md_reg[0] = 0x3d04,
2515 .md_reg[1] = 0x3d08,
2516 .bank_reg = 0x3d00,
2517 .mn[0] = {
2533 .s[0] = {
2534 .src_sel_shift = 0,
2538 .src_sel_shift = 0,
2541 .p[0] = {
2549 .mux_sel_bit = 0,
2552 .enable_reg = 0x3d00,
2564 .halt_reg = 0x3c20,
2566 .hwcg_reg = 0x3d14,
2569 .enable_reg = 0x3d14,
2584 { 266000000, P_PLL0, 3, 0, 0 },
2585 { 400000000, P_PLL0, 2, 0, 0 },
2590 .ns_reg[0] = 0x3dc4,
2591 .ns_reg[1] = 0x3dc8,
2592 .bank_reg = 0x3dc0,
2593 .s[0] = {
2594 .src_sel_shift = 0,
2598 .src_sel_shift = 0,
2601 .p[0] = {
2609 .mux_sel_bit = 0,
2612 .enable_reg = 0x3dc0,
2624 .halt_reg = 0x3c20,
2627 .enable_reg = 0x3dd0,
2643 { 275000000, P_PLL18, 2, 0, 0 },
2644 { 550000000, P_PLL18, 1, 0, 0 },
2645 { 733000000, P_PLL18, 1, 0, 0 },
2650 .ns_reg[0] = 0x3d2c,
2651 .ns_reg[1] = 0x3d30,
2652 .md_reg[0] = 0x3d24,
2653 .md_reg[1] = 0x3d28,
2654 .bank_reg = 0x3d20,
2655 .mn[0] = {
2671 .s[0] = {
2672 .src_sel_shift = 0,
2676 .src_sel_shift = 0,
2679 .p[0] = {
2687 .mux_sel_bit = 0,
2690 .enable_reg = 0x3d20,
2703 .ns_reg[0] = 0x3d4c,
2704 .ns_reg[1] = 0x3d50,
2705 .md_reg[0] = 0x3d44,
2706 .md_reg[1] = 0x3d48,
2707 .bank_reg = 0x3d40,
2708 .mn[0] = {
2724 .s[0] = {
2725 .src_sel_shift = 0,
2729 .src_sel_shift = 0,
2732 .p[0] = {
2740 .mux_sel_bit = 0,
2743 .enable_reg = 0x3d40,
2879 [QDSS_STM_RESET] = { 0x2060, 6 },
2880 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2881 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2882 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2883 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2884 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2885 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2886 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2887 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2888 [ADM0_C2_RESET] = { 0x220c, 4 },
2889 [ADM0_C1_RESET] = { 0x220c, 3 },
2890 [ADM0_C0_RESET] = { 0x220c, 2 },
2891 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2892 [ADM0_RESET] = { 0x220c, 0 },
2893 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2894 [QDSS_POR_RESET] = { 0x2260, 4 },
2895 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2896 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2897 [QDSS_AXI_RESET] = { 0x2260, 1 },
2898 [QDSS_DBG_RESET] = { 0x2260, 0 },
2899 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2900 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2901 [PCIE_EXT_RESET] = { 0x22dc, 6 },
2902 [PCIE_PHY_RESET] = { 0x22dc, 5 },
2903 [PCIE_PCI_RESET] = { 0x22dc, 4 },
2904 [PCIE_POR_RESET] = { 0x22dc, 3 },
2905 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2906 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2907 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2908 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2909 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2910 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2911 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2912 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2913 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2914 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2915 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2916 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2917 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2918 [PPSS_PROC_RESET] = { 0x2594, 1 },
2919 [PPSS_RESET] = { 0x2594, 0 },
2920 [DMA_BAM_RESET] = { 0x25c0, 7 },
2921 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2922 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2923 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2924 [TSIF_H_RESET] = { 0x2700, 7 },
2925 [CE1_H_RESET] = { 0x2720, 7 },
2926 [CE1_CORE_RESET] = { 0x2724, 7 },
2927 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2928 [CE2_H_RESET] = { 0x2740, 7 },
2929 [CE2_CORE_RESET] = { 0x2744, 7 },
2930 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2931 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2932 [RPM_PROC_RESET] = { 0x27c0, 7 },
2933 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2934 [SDC1_RESET] = { 0x2830, 0 },
2935 [SDC2_RESET] = { 0x2850, 0 },
2936 [SDC3_RESET] = { 0x2870, 0 },
2937 [SDC4_RESET] = { 0x2890, 0 },
2938 [USB_HS1_RESET] = { 0x2910, 0 },
2939 [USB_HSIC_RESET] = { 0x2934, 0 },
2940 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2941 [USB_FS1_RESET] = { 0x2974, 0 },
2942 [GSBI1_RESET] = { 0x29dc, 0 },
2943 [GSBI2_RESET] = { 0x29fc, 0 },
2944 [GSBI3_RESET] = { 0x2a1c, 0 },
2945 [GSBI4_RESET] = { 0x2a3c, 0 },
2946 [GSBI5_RESET] = { 0x2a5c, 0 },
2947 [GSBI6_RESET] = { 0x2a7c, 0 },
2948 [GSBI7_RESET] = { 0x2a9c, 0 },
2949 [SPDM_RESET] = { 0x2b6c, 0 },
2950 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2951 [TLMM_H_RESET] = { 0x2ba0, 7 },
2952 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2953 [SATA_RESET] = { 0x2c1c, 0 },
2954 [TSSC_RESET] = { 0x2ca0, 7 },
2955 [PDM_RESET] = { 0x2cc0, 12 },
2956 [MPM_H_RESET] = { 0x2da0, 7 },
2957 [MPM_RESET] = { 0x2da4, 0 },
2958 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2959 [PRNG_RESET] = { 0x2e80, 12 },
2960 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2961 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2962 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2963 [PCIE_1_M_RESET] = { 0x3a98, 1 },
2964 [PCIE_1_S_RESET] = { 0x3a98, 0 },
2965 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2966 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2967 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2968 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2969 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2970 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2971 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2972 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2973 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2974 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2975 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2976 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2977 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2978 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2979 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2980 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2981 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2982 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2983 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2984 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2985 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2986 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2987 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2988 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2989 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2990 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2991 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2992 [NSSFB0_RESET] = { 0x3b60, 6 },
2993 [NSSFB1_RESET] = { 0x3b60, 7 },
2994 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
2995 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
2996 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
2997 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
2998 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
2999 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
3000 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
3001 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
3002 [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
3003 [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
3004 [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
3005 [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
3006 [GMAC_AHB_RESET] = { 0x3e24, 0 },
3007 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
3008 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
3009 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
3010 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
3011 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
3012 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
3013 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
3014 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
3015 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
3016 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
3017 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
3018 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
3019 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
3020 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
3021 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
3022 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
3023 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
3024 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
3025 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
3026 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
3027 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
3028 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
3029 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
3030 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
3031 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
3032 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
3033 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
3034 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
3035 [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
3042 .max_register = 0x3e40,
3083 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); in gcc_ipq806x_probe()
3084 regmap_write(regmap, 0x31b0, 0x3080); in gcc_ipq806x_probe()
3087 regmap_write(regmap, 0x3cb8, 8); in gcc_ipq806x_probe()
3088 regmap_write(regmap, 0x3cd8, 8); in gcc_ipq806x_probe()
3089 regmap_write(regmap, 0x3cf8, 8); in gcc_ipq806x_probe()
3090 regmap_write(regmap, 0x3d18, 8); in gcc_ipq806x_probe()