Lines Matching +full:0 +full:x1740
40 { P_XO, 0 },
50 { P_XO, 0 },
62 { P_XO, 0 },
72 { P_XO, 0 },
82 { P_XO, 0 },
92 { P_XO, 0 },
102 .l_reg = 0x0004,
103 .m_reg = 0x0008,
104 .n_reg = 0x000c,
105 .config_reg = 0x0014,
106 .mode_reg = 0x0000,
107 .status_reg = 0x001c,
118 .enable_reg = 0x1480,
119 .enable_mask = BIT(0),
129 .cmd_rcgr = 0x0150,
141 .cmd_rcgr = 0x0190,
153 .cmd_rcgr = 0x0120,
165 .l_reg = 0x0044,
166 .m_reg = 0x0048,
167 .n_reg = 0x004c,
168 .config_reg = 0x0054,
169 .mode_reg = 0x0040,
170 .status_reg = 0x005c,
181 .enable_reg = 0x1480,
192 .l_reg = 0x1dc4,
193 .m_reg = 0x1dc8,
194 .n_reg = 0x1dcc,
195 .config_reg = 0x1dd4,
196 .mode_reg = 0x1dc0,
197 .status_reg = 0x1ddc,
208 .enable_reg = 0x1480,
219 F(100000000, P_GPLL0, 6, 0, 0),
220 F(200000000, P_GPLL0, 3, 0, 0),
221 F(240000000, P_GPLL0, 2.5, 0, 0),
226 .cmd_rcgr = 0x1d64,
245 .cmd_rcgr = 0x03d4,
264 .cmd_rcgr = 0x1bd4,
278 .halt_reg = 0x1bd0,
280 .enable_reg = 0x1bd0,
281 .enable_mask = BIT(0),
295 .halt_reg = 0x1bcc,
297 .enable_reg = 0x1bcc,
298 .enable_mask = BIT(0),
312 F(19200000, P_XO, 1, 0, 0),
313 F(50000000, P_GPLL0, 12, 0, 0),
318 .cmd_rcgr = 0x0660,
332 F(4800000, P_XO, 4, 0, 0),
333 F(9600000, P_XO, 2, 0, 0),
335 F(19200000, P_XO, 1, 0, 0),
337 F(50000000, P_GPLL0, 12, 0, 0),
342 .cmd_rcgr = 0x064c,
356 .cmd_rcgr = 0x06e0,
369 .cmd_rcgr = 0x06cc,
383 .cmd_rcgr = 0x0760,
396 .cmd_rcgr = 0x074c,
410 .cmd_rcgr = 0x07e0,
423 .cmd_rcgr = 0x07cc,
437 .cmd_rcgr = 0x0860,
450 .cmd_rcgr = 0x084c,
464 .cmd_rcgr = 0x08e0,
477 .cmd_rcgr = 0x08cc,
495 F(19200000, P_XO, 1, 0, 0),
498 F(40000000, P_GPLL0, 15, 0, 0),
500 F(48000000, P_GPLL0, 12.5, 0, 0),
504 F(60000000, P_GPLL0, 10, 0, 0),
505 F(63160000, P_GPLL0, 9.5, 0, 0),
510 .cmd_rcgr = 0x068c,
524 .cmd_rcgr = 0x070c,
538 .cmd_rcgr = 0x078c,
552 .cmd_rcgr = 0x080c,
566 .cmd_rcgr = 0x088c,
580 .cmd_rcgr = 0x090c,
594 .cmd_rcgr = 0x09a0,
607 .cmd_rcgr = 0x098c,
621 .cmd_rcgr = 0x0a20,
634 .cmd_rcgr = 0x0a0c,
648 .cmd_rcgr = 0x0aa0,
661 .cmd_rcgr = 0x0a8c,
675 .cmd_rcgr = 0x0b20,
688 .cmd_rcgr = 0x0b0c,
702 .cmd_rcgr = 0x0ba0,
715 .cmd_rcgr = 0x0b8c,
729 .cmd_rcgr = 0x0c20,
742 .cmd_rcgr = 0x0c0c,
756 .cmd_rcgr = 0x09cc,
770 .cmd_rcgr = 0x0a4c,
784 .cmd_rcgr = 0x0acc,
798 .cmd_rcgr = 0x0b4c,
812 .cmd_rcgr = 0x0bcc,
826 .cmd_rcgr = 0x0c4c,
840 F(50000000, P_GPLL0, 12, 0, 0),
841 F(85710000, P_GPLL0, 7, 0, 0),
842 F(100000000, P_GPLL0, 6, 0, 0),
843 F(171430000, P_GPLL0, 3.5, 0, 0),
848 .cmd_rcgr = 0x1050,
861 F(50000000, P_GPLL0, 12, 0, 0),
862 F(85710000, P_GPLL0, 7, 0, 0),
863 F(100000000, P_GPLL0, 6, 0, 0),
864 F(171430000, P_GPLL0, 3.5, 0, 0),
869 .cmd_rcgr = 0x1090,
882 F(50000000, P_GPLL0, 12, 0, 0),
883 F(85710000, P_GPLL0, 7, 0, 0),
884 F(100000000, P_GPLL0, 6, 0, 0),
885 F(171430000, P_GPLL0, 3.5, 0, 0),
890 .cmd_rcgr = 0x1d10,
903 F(19200000, P_XO, 1, 0, 0),
904 F(100000000, P_GPLL0, 6, 0, 0),
905 F(200000000, P_GPLL0, 3, 0, 0),
910 .cmd_rcgr = 0x1904,
924 .cmd_rcgr = 0x1944,
938 .cmd_rcgr = 0x1984,
957 .cmd_rcgr = 0x1b2c,
971 .cmd_rcgr = 0x1bac,
985 F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
986 F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
991 .cmd_rcgr = 0x1b18,
1004 .cmd_rcgr = 0x1b98,
1017 F(60000000, P_GPLL0, 10, 0, 0),
1022 .cmd_rcgr = 0x0cd0,
1035 F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1036 F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1037 F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1042 .cmd_rcgr = 0x1c94,
1055 F(19200000, P_XO, 1, 0, 0),
1056 F(50000000, P_GPLL0, 12, 0, 0),
1057 F(100000000, P_GPLL0, 6, 0, 0),
1062 .cmd_rcgr = 0x1c80,
1075 F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1076 F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1077 F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1082 .cmd_rcgr = 0x1ca8,
1095 F(100000000, P_GPLL0, 6, 0, 0),
1100 .cmd_rcgr = 0x1c5c,
1117 F(50000000, P_GPLL0, 12, 0, 0),
1118 F(100000000, P_GPLL0, 6, 0, 0),
1119 F(192000000, P_GPLL4, 4, 0, 0),
1120 F(200000000, P_GPLL0, 3, 0, 0),
1121 F(384000000, P_GPLL4, 2, 0, 0),
1126 .cmd_rcgr = 0x04d0,
1140 .cmd_rcgr = 0x0510,
1154 .cmd_rcgr = 0x0550,
1168 .cmd_rcgr = 0x0590,
1187 .cmd_rcgr = 0x0d90,
1201 F(60000000, P_GPLL0, 10, 0, 0),
1206 .cmd_rcgr = 0x03e8,
1224 .cmd_rcgr = 0x1be8,
1237 F(75000000, P_GPLL0, 8, 0, 0),
1242 .cmd_rcgr = 0x0490,
1255 F(480000000, P_GPLL1, 1, 0, 0),
1260 { P_XO, 0 },
1265 .cmd_rcgr = 0x0440,
1281 F(60000000, P_GPLL1, 8, 0, 0),
1286 .cmd_rcgr = 0x046c,
1303 F(9600000, P_XO, 2, 0, 0),
1308 .cmd_rcgr = 0x0458,
1321 .halt_reg = 0x1f14,
1323 .enable_reg = 0x1f14,
1324 .enable_mask = BIT(0),
1338 F(60000000, P_GPLL0, 10, 0, 0),
1343 .cmd_rcgr = 0x1f00,
1356 F(75000000, P_GPLL0, 8, 0, 0),
1361 .cmd_rcgr = 0x041c,
1374 .halt_reg = 0x0d44,
1377 .enable_reg = 0x1484,
1391 .halt_reg = 0x05c4,
1394 .enable_reg = 0x1484,
1408 .halt_reg = 0x0648,
1410 .enable_reg = 0x0648,
1411 .enable_mask = BIT(0),
1425 .halt_reg = 0x0644,
1427 .enable_reg = 0x0644,
1428 .enable_mask = BIT(0),
1442 .halt_reg = 0x06c8,
1444 .enable_reg = 0x06c8,
1445 .enable_mask = BIT(0),
1459 .halt_reg = 0x06c4,
1461 .enable_reg = 0x06c4,
1462 .enable_mask = BIT(0),
1476 .halt_reg = 0x0748,
1478 .enable_reg = 0x0748,
1479 .enable_mask = BIT(0),
1493 .halt_reg = 0x0744,
1495 .enable_reg = 0x0744,
1496 .enable_mask = BIT(0),
1510 .halt_reg = 0x07c8,
1512 .enable_reg = 0x07c8,
1513 .enable_mask = BIT(0),
1527 .halt_reg = 0x07c4,
1529 .enable_reg = 0x07c4,
1530 .enable_mask = BIT(0),
1544 .halt_reg = 0x0848,
1546 .enable_reg = 0x0848,
1547 .enable_mask = BIT(0),
1561 .halt_reg = 0x0844,
1563 .enable_reg = 0x0844,
1564 .enable_mask = BIT(0),
1578 .halt_reg = 0x08c8,
1580 .enable_reg = 0x08c8,
1581 .enable_mask = BIT(0),
1595 .halt_reg = 0x08c4,
1597 .enable_reg = 0x08c4,
1598 .enable_mask = BIT(0),
1612 .halt_reg = 0x0684,
1614 .enable_reg = 0x0684,
1615 .enable_mask = BIT(0),
1629 .halt_reg = 0x0704,
1631 .enable_reg = 0x0704,
1632 .enable_mask = BIT(0),
1646 .halt_reg = 0x0784,
1648 .enable_reg = 0x0784,
1649 .enable_mask = BIT(0),
1663 .halt_reg = 0x0804,
1665 .enable_reg = 0x0804,
1666 .enable_mask = BIT(0),
1680 .halt_reg = 0x0884,
1682 .enable_reg = 0x0884,
1683 .enable_mask = BIT(0),
1697 .halt_reg = 0x0904,
1699 .enable_reg = 0x0904,
1700 .enable_mask = BIT(0),
1714 .halt_reg = 0x0944,
1717 .enable_reg = 0x1484,
1731 .halt_reg = 0x0988,
1733 .enable_reg = 0x0988,
1734 .enable_mask = BIT(0),
1748 .halt_reg = 0x0984,
1750 .enable_reg = 0x0984,
1751 .enable_mask = BIT(0),
1765 .halt_reg = 0x0a08,
1767 .enable_reg = 0x0a08,
1768 .enable_mask = BIT(0),
1782 .halt_reg = 0x0a04,
1784 .enable_reg = 0x0a04,
1785 .enable_mask = BIT(0),
1799 .halt_reg = 0x0a88,
1801 .enable_reg = 0x0a88,
1802 .enable_mask = BIT(0),
1816 .halt_reg = 0x0a84,
1818 .enable_reg = 0x0a84,
1819 .enable_mask = BIT(0),
1833 .halt_reg = 0x0b08,
1835 .enable_reg = 0x0b08,
1836 .enable_mask = BIT(0),
1850 .halt_reg = 0x0b04,
1852 .enable_reg = 0x0b04,
1853 .enable_mask = BIT(0),
1867 .halt_reg = 0x0b88,
1869 .enable_reg = 0x0b88,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0x0b84,
1886 .enable_reg = 0x0b84,
1887 .enable_mask = BIT(0),
1901 .halt_reg = 0x0c08,
1903 .enable_reg = 0x0c08,
1904 .enable_mask = BIT(0),
1918 .halt_reg = 0x0c04,
1920 .enable_reg = 0x0c04,
1921 .enable_mask = BIT(0),
1935 .halt_reg = 0x09c4,
1937 .enable_reg = 0x09c4,
1938 .enable_mask = BIT(0),
1952 .halt_reg = 0x0a44,
1954 .enable_reg = 0x0a44,
1955 .enable_mask = BIT(0),
1969 .halt_reg = 0x0ac4,
1971 .enable_reg = 0x0ac4,
1972 .enable_mask = BIT(0),
1986 .halt_reg = 0x0b44,
1988 .enable_reg = 0x0b44,
1989 .enable_mask = BIT(0),
2003 .halt_reg = 0x0bc4,
2005 .enable_reg = 0x0bc4,
2006 .enable_mask = BIT(0),
2020 .halt_reg = 0x0c44,
2022 .enable_reg = 0x0c44,
2023 .enable_mask = BIT(0),
2037 .halt_reg = 0x0e04,
2040 .enable_reg = 0x1484,
2054 .halt_reg = 0x104c,
2057 .enable_reg = 0x1484,
2071 .halt_reg = 0x1048,
2074 .enable_reg = 0x1484,
2088 .halt_reg = 0x1050,
2091 .enable_reg = 0x1484,
2106 .halt_reg = 0x108c,
2109 .enable_reg = 0x1484,
2110 .enable_mask = BIT(0),
2123 .halt_reg = 0x1088,
2126 .enable_reg = 0x1484,
2140 .halt_reg = 0x1090,
2143 .enable_reg = 0x1484,
2158 .halt_reg = 0x1d0c,
2161 .enable_reg = 0x1d0c,
2162 .enable_mask = BIT(0),
2175 .halt_reg = 0x1088,
2178 .enable_reg = 0x1d08,
2179 .enable_mask = BIT(0),
2192 .halt_reg = 0x1090,
2195 .enable_reg = 0x1d04,
2196 .enable_mask = BIT(0),
2210 .halt_reg = 0x1900,
2212 .enable_reg = 0x1900,
2213 .enable_mask = BIT(0),
2227 .halt_reg = 0x1940,
2229 .enable_reg = 0x1940,
2230 .enable_mask = BIT(0),
2244 .halt_reg = 0x1980,
2246 .enable_reg = 0x1980,
2247 .enable_mask = BIT(0),
2261 .halt_reg = 0x0248,
2263 .enable_reg = 0x0248,
2264 .enable_mask = BIT(0),
2277 .halt_reg = 0x1b10,
2279 .enable_reg = 0x1b10,
2280 .enable_mask = BIT(0),
2294 .halt_reg = 0x1b0c,
2296 .enable_reg = 0x1b0c,
2297 .enable_mask = BIT(0),
2311 .halt_reg = 0x1b08,
2313 .enable_reg = 0x1b08,
2314 .enable_mask = BIT(0),
2328 .halt_reg = 0x1b14,
2330 .enable_reg = 0x1b14,
2331 .enable_mask = BIT(0),
2345 .halt_reg = 0x1b04,
2347 .enable_reg = 0x1b04,
2348 .enable_mask = BIT(0),
2362 .halt_reg = 0x1b90,
2364 .enable_reg = 0x1b90,
2365 .enable_mask = BIT(0),
2379 .halt_reg = 0x1b8c,
2381 .enable_reg = 0x1b8c,
2382 .enable_mask = BIT(0),
2396 .halt_reg = 0x1b88,
2398 .enable_reg = 0x1b88,
2399 .enable_mask = BIT(0),
2413 .halt_reg = 0x1b94,
2415 .enable_reg = 0x1b94,
2416 .enable_mask = BIT(0),
2430 .halt_reg = 0x1b84,
2432 .enable_reg = 0x1b84,
2433 .enable_mask = BIT(0),
2447 .halt_reg = 0x0ccc,
2449 .enable_reg = 0x0ccc,
2450 .enable_mask = BIT(0),
2464 .halt_reg = 0x0cc4,
2466 .enable_reg = 0x0cc4,
2467 .enable_mask = BIT(0),
2480 .halt_reg = 0x01a4,
2482 .enable_reg = 0x01a4,
2483 .enable_mask = BIT(0),
2497 .halt_reg = 0x0d04,
2500 .enable_reg = 0x1484,
2514 .halt_reg = 0x1c54,
2516 .enable_reg = 0x1c54,
2517 .enable_mask = BIT(0),
2531 .halt_reg = 0x1c44,
2533 .enable_reg = 0x1c44,
2534 .enable_mask = BIT(0),
2548 .halt_reg = 0x1c48,
2550 .enable_reg = 0x1c48,
2551 .enable_mask = BIT(0),
2565 .halt_reg = 0x1c50,
2567 .enable_reg = 0x1c50,
2568 .enable_mask = BIT(0),
2582 .halt_reg = 0x1c58,
2584 .enable_reg = 0x1c58,
2585 .enable_mask = BIT(0),
2599 .halt_reg = 0x1c4c,
2601 .enable_reg = 0x1c4c,
2602 .enable_mask = BIT(0),
2616 .halt_reg = 0x04c8,
2618 .enable_reg = 0x04c8,
2619 .enable_mask = BIT(0),
2632 .halt_reg = 0x04c4,
2634 .enable_reg = 0x04c4,
2635 .enable_mask = BIT(0),
2649 .halt_reg = 0x04e8,
2651 .enable_reg = 0x04e8,
2652 .enable_mask = BIT(0),
2665 .halt_reg = 0x04e4,
2667 .enable_reg = 0x04e4,
2668 .enable_mask = BIT(0),
2681 .halt_reg = 0x0508,
2683 .enable_reg = 0x0508,
2684 .enable_mask = BIT(0),
2697 .halt_reg = 0x0504,
2699 .enable_reg = 0x0504,
2700 .enable_mask = BIT(0),
2714 .halt_reg = 0x0548,
2716 .enable_reg = 0x0548,
2717 .enable_mask = BIT(0),
2730 .halt_reg = 0x0544,
2732 .enable_reg = 0x0544,
2733 .enable_mask = BIT(0),
2747 .halt_reg = 0x0588,
2749 .enable_reg = 0x0588,
2750 .enable_mask = BIT(0),
2763 .halt_reg = 0x0584,
2765 .enable_reg = 0x0584,
2766 .enable_mask = BIT(0),
2780 .halt_reg = 0x013c,
2782 .enable_reg = 0x013c,
2783 .enable_mask = BIT(0),
2797 .halt_reg = 0x0108,
2799 .enable_reg = 0x0108,
2800 .enable_mask = BIT(0),
2814 .halt_reg = 0x0138,
2816 .enable_reg = 0x0138,
2817 .enable_mask = BIT(0),
2831 .halt_reg = 0x0d84,
2833 .enable_reg = 0x0d84,
2834 .enable_mask = BIT(0),
2847 .halt_reg = 0x0d8c,
2849 .enable_reg = 0x0d8c,
2850 .enable_mask = BIT(0),
2864 .halt_reg = 0x0d88,
2866 .enable_reg = 0x0d88,
2867 .enable_mask = BIT(0),
2881 .halt_reg = 0x1d48,
2883 .enable_reg = 0x1d48,
2884 .enable_mask = BIT(0),
2898 .halt_reg = 0x1d44,
2900 .enable_reg = 0x1d44,
2901 .enable_mask = BIT(0),
2915 .halt_reg = 0x1d50,
2917 .enable_reg = 0x1d50,
2918 .enable_mask = BIT(0),
2932 .halt_reg = 0x1d5c,
2934 .enable_reg = 0x1d5c,
2935 .enable_mask = BIT(0),
2949 .halt_reg = 0x1d60,
2951 .enable_reg = 0x1d60,
2952 .enable_mask = BIT(0),
2966 .halt_reg = 0x1d4c,
2968 .enable_reg = 0x1d4c,
2969 .enable_mask = BIT(0),
2983 .halt_reg = 0x1d54,
2985 .enable_reg = 0x1d54,
2986 .enable_mask = BIT(0),
3000 .halt_reg = 0x1d58,
3002 .enable_reg = 0x1d58,
3003 .enable_mask = BIT(0),
3017 .halt_reg = 0x04ac,
3019 .enable_reg = 0x04ac,
3020 .enable_mask = BIT(0),
3033 .halt_reg = 0x04b4,
3035 .enable_reg = 0x04b4,
3036 .enable_mask = BIT(0),
3049 .halt_reg = 0x03c8,
3051 .enable_reg = 0x03c8,
3052 .enable_mask = BIT(0),
3066 .halt_reg = 0x1bc8,
3068 .enable_reg = 0x1bc8,
3069 .enable_mask = BIT(0),
3083 .halt_reg = 0x03d0,
3085 .enable_reg = 0x03d0,
3086 .enable_mask = BIT(0),
3100 .halt_reg = 0x03cc,
3102 .enable_reg = 0x03cc,
3103 .enable_mask = BIT(0),
3116 .halt_reg = 0x0488,
3118 .enable_reg = 0x0488,
3119 .enable_mask = BIT(0),
3132 .halt_reg = 0x048c,
3134 .enable_reg = 0x048c,
3135 .enable_mask = BIT(0),
3149 .halt_reg = 0x0484,
3151 .enable_reg = 0x0484,
3152 .enable_mask = BIT(0),
3166 .halt_reg = 0x0408,
3168 .enable_reg = 0x0408,
3169 .enable_mask = BIT(0),
3182 .halt_reg = 0x0410,
3184 .enable_reg = 0x0410,
3185 .enable_mask = BIT(0),
3199 .halt_reg = 0x0414,
3201 .enable_reg = 0x0414,
3202 .enable_mask = BIT(0),
3216 .halt_reg = 0x0418,
3218 .enable_reg = 0x0418,
3219 .enable_mask = BIT(0),
3232 .halt_reg = 0x040c,
3234 .enable_reg = 0x040c,
3235 .enable_mask = BIT(0),
3249 .gdscr = 0x404,
3257 .gdscr = 0x1ac4,
3265 .gdscr = 0x1b44,
3273 .gdscr = 0x1e84,
3481 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3482 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
3483 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
3484 [GCC_IMEM_BCR] = { 0x0200 },
3485 [GCC_MMSS_BCR] = { 0x0240 },
3486 [GCC_QDSS_BCR] = { 0x0300 },
3487 [GCC_USB_30_BCR] = { 0x03c0 },
3488 [GCC_USB3_PHY_BCR] = { 0x03fc },
3489 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3490 [GCC_USB_HS_BCR] = { 0x0480 },
3491 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
3492 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
3493 [GCC_SDCC1_BCR] = { 0x04c0 },
3494 [GCC_SDCC2_BCR] = { 0x0500 },
3495 [GCC_SDCC3_BCR] = { 0x0540 },
3496 [GCC_SDCC4_BCR] = { 0x0580 },
3497 [GCC_BLSP1_BCR] = { 0x05c0 },
3498 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3499 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
3500 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3501 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
3502 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3503 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
3504 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3505 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
3506 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3507 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
3508 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3509 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
3510 [GCC_BLSP2_BCR] = { 0x0940 },
3511 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3512 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3513 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3514 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3515 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3516 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3517 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3518 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3519 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3520 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3521 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3522 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3523 [GCC_PDM_BCR] = { 0x0cc0 },
3524 [GCC_PRNG_BCR] = { 0x0d00 },
3525 [GCC_BAM_DMA_BCR] = { 0x0d40 },
3526 [GCC_TSIF_BCR] = { 0x0d80 },
3527 [GCC_TCSR_BCR] = { 0x0dc0 },
3528 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
3529 [GCC_MSG_RAM_BCR] = { 0x0e40 },
3530 [GCC_TLMM_BCR] = { 0x0e80 },
3531 [GCC_MPM_BCR] = { 0x0ec0 },
3532 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3533 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3534 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
3535 [GCC_SPMI_BCR] = { 0x0fc0 },
3536 [GCC_SPDM_BCR] = { 0x1000 },
3537 [GCC_CE1_BCR] = { 0x1040 },
3538 [GCC_CE2_BCR] = { 0x1080 },
3539 [GCC_BIMC_BCR] = { 0x1100 },
3540 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3541 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3542 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3543 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3544 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3545 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3546 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3547 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3548 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3549 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3550 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3551 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3552 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3553 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3554 [GCC_DEHR_BCR] = { 0x1300 },
3555 [GCC_RBCPR_BCR] = { 0x1380 },
3556 [GCC_MSS_RESTART] = { 0x1680 },
3557 [GCC_LPASS_RESTART] = { 0x16c0 },
3558 [GCC_WCSS_RESTART] = { 0x1700 },
3559 [GCC_VENUS_RESTART] = { 0x1740 },
3560 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3561 [GCC_SPSS_BCR] = { 0x1a80 },
3562 [GCC_PCIE_0_BCR] = { 0x1ac0 },
3563 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3564 [GCC_PCIE_1_BCR] = { 0x1b40 },
3565 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3566 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3567 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3568 [GCC_SATA_BCR] = { 0x1c40 },
3569 [GCC_CE3_BCR] = { 0x1d00 },
3570 [GCC_UFS_BCR] = { 0x1d40 },
3571 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3578 .max_register = 0x1fc0,