141  * Calculate m/n:d rate
143  *          parent_rate     m
148 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)  in calc_rate()  argument
157 		tmp *= m;  in calc_rate()
169 	u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;  in clk_rcg2_recalc_rate()  local
175 		regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);  in clk_rcg2_recalc_rate()
176 		m &= mask;  in clk_rcg2_recalc_rate()
180 		n += m;  in clk_rcg2_recalc_rate()
189 	return calc_rate(parent_rate, m, n, mode, hid_div);  in clk_rcg2_recalc_rate()
236 			do_div(tmp, f->m);  in _freq_tbl_determine_rate()
277 				RCG_M_OFFSET(rcg), mask, f->m);  in __clk_rcg2_configure()
282 				RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));  in __clk_rcg2_configure()
296 	if (rcg->mnd_width && f->n && (f->m != f->n))  in __clk_rcg2_configure()
363 	u32 notn_m, n, m, d, not2d, mask;  in clk_rcg2_get_duty_cycle()  local
373 	regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);  in clk_rcg2_get_duty_cycle()
376 	if (!not2d && !m && !notn_m) {  in clk_rcg2_get_duty_cycle()
388 	n = (~(notn_m) + m) & mask;  in clk_rcg2_get_duty_cycle()
399 	u32 notn_m, n, m, d, not2d, mask, duty_per;  in clk_rcg2_set_duty_cycle()  local
409 	regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);  in clk_rcg2_set_duty_cycle()
411 	n = (~(notn_m) + m) & mask;  in clk_rcg2_set_duty_cycle()
422 	if ((d / 2) > (n - m))  in clk_rcg2_set_duty_cycle()
423 		d = (n - m) * 2;  in clk_rcg2_set_duty_cycle()
424 	else if ((d / 2) < (m / 2))  in clk_rcg2_set_duty_cycle()
425 		d = m;  in clk_rcg2_set_duty_cycle()
468 static const struct frac_entry frac_table_675m[] = {	/* link rate of 270M */
469 	{ 52, 295 },	/* 119 M */
470 	{ 11, 57 },	/* 130.25 M */
471 	{ 63, 307 },	/* 138.50 M */
472 	{ 11, 50 },	/* 148.50 M */
473 	{ 47, 206 },	/* 154 M */
474 	{ 31, 100 },	/* 205.25 M */
475 	{ 107, 269 },	/* 268.50 M */
479 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
480 	{ 31, 211 },	/* 119 M */
481 	{ 32, 199 },	/* 130.25 M */
482 	{ 63, 307 },	/* 138.50 M */
483 	{ 11, 60 },	/* 148.50 M */
484 	{ 50, 263 },	/* 154 M */
485 	{ 31, 120 },	/* 205.25 M */
486 	{ 119, 359 },	/* 268.50 M */
520 		f.m = frac->num;  in clk_edp_pixel_set_rate()
783 		f.m = frac->num;  in clk_pixel_set_rate()
972 	 * In case clock is disabled, update the CFG, M, N and D registers  in clk_rcg2_shared_set_rate()
1087 		f->m = val;  in clk_rcg2_dfs_populate_freq()
1093 		val += f->m;  in clk_rcg2_dfs_populate_freq()
1097 	f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);  in clk_rcg2_dfs_populate_freq()
1139 	u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;  in clk_rcg2_dfs_recalc_rate()  local
1169 			    rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);  in clk_rcg2_dfs_recalc_rate()
1170 		m &= mask;  in clk_rcg2_dfs_recalc_rate()
1176 		n += m;  in clk_rcg2_dfs_recalc_rate()
1179 	return calc_rate(parent_rate, m, n, mode, pre_div);  in clk_rcg2_dfs_recalc_rate()
1265 		f.m = num;  in clk_rcg2_dp_set_rate()
1268 		f.m = 0;  in clk_rcg2_dp_set_rate()