Lines Matching full:pll
12 #include "clk-alpha-pll.h"
165 /* TRION PLL specific settings and offsets */
169 /* LUCID PLL specific settings and offsets */
172 /* LUCID 5LPE PLL specific settings and offsets */
178 /* ZONDA PLL specific */
195 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
201 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
203 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
208 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
223 #define wait_for_pll_enable_active(pll) \ argument
224 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
226 #define wait_for_pll_enable_lock(pll) \ argument
227 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
229 #define wait_for_zonda_pll_freq_lock(pll) \ argument
230 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
232 #define wait_for_pll_disable(pll) \ argument
233 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
235 #define wait_for_pll_offline(pll) \ argument
236 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
238 #define wait_for_pll_update(pll) \ argument
239 wait_for_pll(pll, PLL_UPDATE, 1, "update")
241 #define wait_for_pll_update_ack_set(pll) \ argument
242 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
244 #define wait_for_pll_update_ack_clear(pll) \ argument
245 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
254 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
259 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
260 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
261 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
263 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
264 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
267 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
268 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
288 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
290 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
291 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
298 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
301 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
307 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
310 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
317 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
323 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
326 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
330 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
331 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
336 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
342 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
347 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
353 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
356 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
376 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
380 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
389 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
396 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
408 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
413 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
417 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
428 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
431 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
442 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
449 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
487 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
489 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
490 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
504 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
505 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
507 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
509 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
511 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
513 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
528 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
533 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
535 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
536 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
543 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
544 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
545 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
547 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
550 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
554 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
556 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
561 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
565 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
571 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
574 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
575 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
578 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
585 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
587 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
591 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
592 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
593 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
598 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
604 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
606 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
609 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
614 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
617 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
637 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
638 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
643 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
646 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
647 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
703 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
706 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
707 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
710 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
756 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
761 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
764 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
767 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
777 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
780 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
783 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
784 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
787 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
790 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
804 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
810 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
811 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
820 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
822 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
827 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
828 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
832 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
841 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
845 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
847 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
851 /* Enable the PLL outputs */ in clk_trion_pll_enable()
852 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
857 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
858 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
864 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
865 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
869 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
879 /* Disable the global PLL output */ in clk_trion_pll_disable()
880 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
884 /* Disable the PLL outputs */ in clk_trion_pll_disable()
885 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
890 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
891 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
892 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
898 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
899 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
901 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
902 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
957 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
960 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
963 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
988 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
991 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
997 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1004 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1007 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1010 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1022 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1028 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1029 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1046 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1051 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1052 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1053 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1055 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1057 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1059 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1061 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1063 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1069 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1072 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1075 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1082 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1084 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1086 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1095 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1098 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1102 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1106 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1110 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1114 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1119 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1123 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1127 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1132 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1139 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1141 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1143 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1153 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1158 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1162 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1163 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1169 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1170 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1172 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1173 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1200 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1211 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1212 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1214 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1219 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1223 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1228 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1229 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1237 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1239 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1243 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1244 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1257 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1258 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1260 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1263 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1295 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1299 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1303 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1304 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1306 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1307 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1308 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1319 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1320 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1323 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1325 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1326 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1328 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1329 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1330 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1342 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1344 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1345 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1352 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1353 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1357 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1358 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1359 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1364 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1365 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_trion_pll_postdiv_set_rate()
1379 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1381 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1382 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1388 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1392 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1395 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1403 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1404 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1405 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1410 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1411 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1412 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1423 * clk_lucid_pll_configure - configure the lucid pll
1425 * @pll: clk alpha pll
1427 * @config: configuration to apply for pll
1429 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1432 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1433 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1434 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1435 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1437 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1439 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1441 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1443 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1445 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1447 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1449 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1451 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1454 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1457 /* Disable PLL output */ in clk_trion_pll_configure()
1458 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1461 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1463 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1464 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1469 * The TRION PLL requires a power-on self-calibration which happens when the
1470 * PLL comes out of reset. Calibrate in case it is not completed.
1474 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1479 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1504 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1506 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1516 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __alpha_pll_trion_set_rate()
1517 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1519 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1520 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1526 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1528 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1533 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1538 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1543 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1583 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1586 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1587 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1588 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1590 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1592 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1594 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1596 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1604 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1605 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1616 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1617 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1620 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1637 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1641 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1650 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1653 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1654 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); in alpha_pll_lucid_5lpe_enable()
1658 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1662 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1664 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1668 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1669 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1673 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1674 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1679 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
1683 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
1693 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
1694 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
1698 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
1699 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
1703 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
1704 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
1708 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1709 * when the PLL comes out of reset. Calibrate in case it is not completed.
1713 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
1719 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
1747 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_lucid_5lpe_pll_postdiv_set_rate() local
1752 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_lucid_5lpe_pll_postdiv_set_rate()
1755 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_lucid_5lpe_pll_postdiv_set_rate()
1763 for (i = 0; i < pll->num_post_div; i++) { in clk_lucid_5lpe_pll_postdiv_set_rate()
1764 if (pll->post_div_table[i].div == div) { in clk_lucid_5lpe_pll_postdiv_set_rate()
1765 val = pll->post_div_table[i].val; in clk_lucid_5lpe_pll_postdiv_set_rate()
1770 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in clk_lucid_5lpe_pll_postdiv_set_rate()
1771 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_lucid_5lpe_pll_postdiv_set_rate()
1772 mask, val << pll->post_div_shift); in clk_lucid_5lpe_pll_postdiv_set_rate()
1802 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
1805 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
1806 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
1807 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
1808 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
1809 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
1810 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
1811 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
1812 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
1813 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
1814 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
1815 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
1817 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
1819 /* Disable PLL output */ in clk_zonda_pll_configure()
1820 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
1823 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
1825 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
1826 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
1832 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
1833 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
1837 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
1844 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
1847 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
1848 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
1856 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
1859 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
1861 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
1865 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
1867 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
1871 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
1872 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
1874 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
1875 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
1882 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
1883 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
1886 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
1894 /* Disable the global PLL output */ in clk_zonda_pll_disable()
1895 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
1897 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
1898 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
1900 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
1901 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
1903 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
1904 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
1910 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
1913 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
1923 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
1924 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
1930 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
1934 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
1936 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
1940 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()