Lines Matching +full:0 +full:xa010
36 { 600000000, 3300000000UL, 0 },
40 { 249600000, 2000000000UL, 0 },
45 .l = 0x1f,
46 .alpha = 0x4000,
47 .config_ctl_val = 0x20485699,
48 .config_ctl_hi_val = 0x00002067,
49 .test_ctl_val = 0x40000000,
50 .user_ctl_hi_val = 0x00004805,
51 .user_ctl_val = 0x00000001,
55 .offset = 0x0,
73 .l = 0x2a,
74 .alpha = 0x1555,
75 .config_ctl_val = 0x20485699,
76 .config_ctl_hi_val = 0x00002067,
77 .test_ctl_val = 0x40000000,
78 .user_ctl_hi_val = 0x00004805,
82 .offset = 0x1000,
100 .l = 0x64,
101 .config_ctl_val = 0x20000800,
102 .config_ctl_hi_val = 0x400003D2,
103 .test_ctl_val = 0x04000400,
104 .test_ctl_hi_val = 0x00004000,
105 .user_ctl_val = 0x0000030F,
109 .offset = 0x2000,
137 { 0x3, 4 },
142 .offset = 0x2000,
161 .l = 0x38,
162 .alpha = 0x4000,
163 .config_ctl_val = 0x20485699,
164 .config_ctl_hi_val = 0x00002067,
165 .test_ctl_val = 0x40000000,
166 .user_ctl_hi_val = 0x00004805,
170 .offset = 0x3000,
187 { P_BI_TCXO, 0 },
201 { P_BI_TCXO, 0 },
213 { P_BI_TCXO, 0 },
229 { P_BI_TCXO, 0 },
247 { P_BI_TCXO, 0 },
261 { P_BI_TCXO, 0 },
273 { P_BI_TCXO, 0 },
289 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
290 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
291 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
292 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
293 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
298 .cmd_rcgr = 0x6010,
299 .mnd_width = 0,
312 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
313 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
314 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
319 .cmd_rcgr = 0xb0d8,
333 .cmd_rcgr = 0xb14c,
347 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
348 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
349 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
354 .cmd_rcgr = 0x9064,
355 .mnd_width = 0,
368 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
373 .cmd_rcgr = 0x5004,
374 .mnd_width = 0,
387 .cmd_rcgr = 0x5028,
388 .mnd_width = 0,
401 .cmd_rcgr = 0x504c,
402 .mnd_width = 0,
415 .cmd_rcgr = 0x5070,
416 .mnd_width = 0,
429 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
430 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
431 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
432 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
437 .cmd_rcgr = 0x603c,
438 .mnd_width = 0,
451 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
452 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
453 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
454 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
455 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
460 .cmd_rcgr = 0xb088,
461 .mnd_width = 0,
474 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
475 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
476 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
477 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
482 .cmd_rcgr = 0x9010,
483 .mnd_width = 0,
496 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
497 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
498 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
499 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
504 .cmd_rcgr = 0x903c,
505 .mnd_width = 0,
518 .cmd_rcgr = 0xa010,
519 .mnd_width = 0,
532 .cmd_rcgr = 0xa034,
533 .mnd_width = 0,
546 .cmd_rcgr = 0xb004,
547 .mnd_width = 0,
561 .cmd_rcgr = 0xb024,
562 .mnd_width = 0,
575 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
576 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
577 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
578 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0),
579 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
584 .cmd_rcgr = 0x7010,
585 .mnd_width = 0,
598 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
599 F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0),
600 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
601 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0),
602 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
607 .cmd_rcgr = 0xb04c,
608 .mnd_width = 0,
621 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
622 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
623 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
624 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
629 .cmd_rcgr = 0xb0f8,
630 .mnd_width = 0,
643 F(19200000, P_BI_TCXO, 1, 0, 0),
645 F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0),
650 .cmd_rcgr = 0x4004,
664 .cmd_rcgr = 0x4024,
678 .cmd_rcgr = 0x4044,
692 .cmd_rcgr = 0x4064,
706 .cmd_rcgr = 0x4084,
720 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
725 .cmd_rcgr = 0x6058,
726 .mnd_width = 0,
740 .halt_reg = 0x6070,
743 .enable_reg = 0x6070,
744 .enable_mask = BIT(0),
758 .halt_reg = 0x6054,
761 .enable_reg = 0x6054,
762 .enable_mask = BIT(0),
776 .halt_reg = 0x6038,
779 .enable_reg = 0x6038,
780 .enable_mask = BIT(0),
789 .halt_reg = 0x6028,
792 .enable_reg = 0x6028,
793 .enable_mask = BIT(0),
807 .halt_reg = 0xb124,
810 .enable_reg = 0xb124,
811 .enable_mask = BIT(0),
820 .halt_reg = 0xb0f0,
823 .enable_reg = 0xb0f0,
824 .enable_mask = BIT(0),
838 .halt_reg = 0xb164,
841 .enable_reg = 0xb164,
842 .enable_mask = BIT(0),
856 .halt_reg = 0xb144,
859 .enable_reg = 0xb144,
860 .enable_mask = BIT(0),
874 .halt_reg = 0xb11c,
877 .enable_reg = 0xb11c,
878 .enable_mask = BIT(0),
892 .halt_reg = 0x501c,
895 .enable_reg = 0x501c,
896 .enable_mask = BIT(0),
910 .halt_reg = 0x5040,
913 .enable_reg = 0x5040,
914 .enable_mask = BIT(0),
928 .halt_reg = 0x5064,
931 .enable_reg = 0x5064,
932 .enable_mask = BIT(0),
946 .halt_reg = 0x5088,
949 .enable_reg = 0x5088,
950 .enable_mask = BIT(0),
964 .halt_reg = 0x5020,
967 .enable_reg = 0x5020,
968 .enable_mask = BIT(0),
982 .halt_reg = 0x5044,
985 .enable_reg = 0x5044,
986 .enable_mask = BIT(0),
1000 .halt_reg = 0x5068,
1003 .enable_reg = 0x5068,
1004 .enable_mask = BIT(0),
1018 .halt_reg = 0x508c,
1021 .enable_reg = 0x508c,
1022 .enable_mask = BIT(0),
1036 .halt_reg = 0xb0a0,
1039 .enable_reg = 0xb0a0,
1040 .enable_mask = BIT(0),
1054 .halt_reg = 0x9080,
1057 .enable_reg = 0x9080,
1058 .enable_mask = BIT(0),
1067 .halt_reg = 0x9028,
1070 .enable_reg = 0x9028,
1071 .enable_mask = BIT(0),
1085 .halt_reg = 0x907c,
1088 .enable_reg = 0x907c,
1089 .enable_mask = BIT(0),
1103 .halt_reg = 0x9054,
1106 .enable_reg = 0x9054,
1107 .enable_mask = BIT(0),
1121 .halt_reg = 0x9038,
1124 .enable_reg = 0x9038,
1125 .enable_mask = BIT(0),
1139 .halt_reg = 0xa058,
1142 .enable_reg = 0xa058,
1143 .enable_mask = BIT(0),
1152 .halt_reg = 0xa028,
1155 .enable_reg = 0xa028,
1156 .enable_mask = BIT(0),
1170 .halt_reg = 0xa054,
1173 .enable_reg = 0xa054,
1174 .enable_mask = BIT(0),
1188 .halt_reg = 0xa04c,
1191 .enable_reg = 0xa04c,
1192 .enable_mask = BIT(0),
1206 .halt_reg = 0xa030,
1209 .enable_reg = 0xa030,
1210 .enable_mask = BIT(0),
1224 .halt_reg = 0xb01c,
1227 .enable_reg = 0xb01c,
1228 .enable_mask = BIT(0),
1242 .halt_reg = 0xb044,
1245 .enable_reg = 0xb044,
1246 .enable_mask = BIT(0),
1260 .halt_reg = 0xb03c,
1263 .enable_reg = 0xb03c,
1264 .enable_mask = BIT(0),
1278 .halt_reg = 0x7040,
1281 .enable_reg = 0x7040,
1282 .enable_mask = BIT(0),
1296 .halt_reg = 0x703c,
1299 .enable_reg = 0x703c,
1300 .enable_mask = BIT(0),
1314 .halt_reg = 0x7038,
1317 .enable_reg = 0x7038,
1318 .enable_mask = BIT(0),
1327 .halt_reg = 0x7028,
1330 .enable_reg = 0x7028,
1331 .enable_mask = BIT(0),
1345 .halt_reg = 0xb064,
1348 .enable_reg = 0xb064,
1349 .enable_mask = BIT(0),
1363 .halt_reg = 0xb110,
1366 .enable_reg = 0xb110,
1367 .enable_mask = BIT(0),
1381 .halt_reg = 0x401c,
1384 .enable_reg = 0x401c,
1385 .enable_mask = BIT(0),
1399 .halt_reg = 0x403c,
1402 .enable_reg = 0x403c,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0x405c,
1420 .enable_reg = 0x405c,
1421 .enable_mask = BIT(0),
1435 .halt_reg = 0x407c,
1438 .enable_reg = 0x407c,
1439 .enable_mask = BIT(0),
1453 .halt_reg = 0x409c,
1456 .enable_reg = 0x409c,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0xb140,
1474 .enable_reg = 0xb140,
1475 .enable_mask = BIT(0),
1484 .halt_reg = 0xb0a8,
1487 .enable_reg = 0xb0a8,
1488 .enable_mask = BIT(0),
1497 .gdscr = 0x6004,
1506 .gdscr = 0x9004,
1514 .gdscr = 0xa004,
1522 .gdscr = 0x7004,
1531 .gdscr = 0xb134,
1630 .max_register = 0xd028,
1656 if (ret < 0) in cam_cc_sc7180_probe()
1660 if (ret < 0) in cam_cc_sc7180_probe()
1664 if (ret < 0) { in cam_cc_sc7180_probe()
1670 if (ret < 0) { in cam_cc_sc7180_probe()
1693 if (ret < 0) { in cam_cc_sc7180_probe()
1698 return 0; in cam_cc_sc7180_probe()