Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
20 #include "clk-regmap.h"
21 #include "clk-pll.h"
22 #include "clk-mpll.h"
56 .data = &(struct meson_clk_pll_data){
59 .shift = 30,
64 .shift = 0,
69 .shift = 9,
74 .shift = 0,
79 .shift = 31,
84 .shift = 29,
94 .index = -1,
101 .data = &(struct clk_regmap_div_data){
103 .shift = 16,
122 .data = &(struct meson_clk_pll_data){
125 .shift = 30,
130 .shift = 0,
135 .shift = 10,
140 .shift = 0,
145 .shift = 31,
150 .shift = 29,
161 .index = -1,
168 .data = &(struct clk_regmap_div_data){
170 .shift = 16,
186 .data = &(struct clk_regmap_div_data){
188 .shift = 18,
204 .data = &(struct meson_clk_pll_data){
207 .shift = 30,
212 .shift = 0,
217 .shift = 9,
222 .shift = 31,
227 .shift = 29,
238 .index = -1,
245 .data = &(struct clk_regmap_div_data){
247 .shift = 16,
276 .data = &(struct clk_regmap_gate_data){
304 .data = &(struct clk_regmap_gate_data){
332 .data = &(struct clk_regmap_gate_data){
360 .data = &(struct clk_regmap_gate_data){
388 .data = &(struct clk_regmap_gate_data){
403 .data = &(struct clk_regmap_div_data){
405 .shift = 12,
419 .data = &(struct meson_clk_mpll_data){
422 .shift = 0,
427 .shift = 15,
432 .shift = 16,
437 .shift = 25,
453 .data = &(struct clk_regmap_gate_data){
469 .data = &(struct meson_clk_mpll_data){
472 .shift = 0,
477 .shift = 15,
482 .shift = 16,
498 .data = &(struct clk_regmap_gate_data){
514 .data = &(struct meson_clk_mpll_data){
517 .shift = 0,
522 .shift = 15,
527 .shift = 16,
543 .data = &(struct clk_regmap_gate_data){
560 .data = &(struct clk_regmap_mux_data){
563 .shift = 12,
584 .data = &(struct clk_regmap_div_data){
586 .shift = 0,
600 .data = &(struct clk_regmap_gate_data){
616 .data = &(struct clk_regmap_mux_data){
619 .shift = 0,
625 { .fw_name = "xtal", .name = "xtal", .index = -1, },
675 .data = &(struct clk_regmap_div_data){
677 .shift = 20,
695 .data = &(struct clk_regmap_mux_data){
698 .shift = 2,
721 .data = &(struct clk_regmap_mux_data){
724 .shift = 7,
730 { .fw_name = "xtal", .name = "xtal", .index = -1, },
741 .data = &(struct clk_regmap_mux_data){
744 .shift = 9,
756 { .fw_name = "xtal", .name = "xtal", .index = -1, },
764 .data = &(struct clk_regmap_div_data){
766 .shift = 0,
782 .data = &(struct clk_regmap_gate_data){
890 .data = &(struct clk_regmap_mux_data){
893 .shift = 3,
913 .data = &(struct clk_regmap_gate_data){
930 .data = &(struct clk_regmap_mux_data){
933 .shift = 6,
952 .data = &(struct clk_regmap_gate_data){
970 .data = &(struct clk_regmap_mux_data){
973 .shift = 9,
993 .data = &(struct clk_regmap_gate_data){
1010 .data = &(struct clk_regmap_mux_data){
1013 .shift = 12,
1032 .data = &(struct clk_regmap_gate_data){
1049 .data = &(struct clk_regmap_mux_data){
1052 .shift = 15,
1072 .data = &(struct clk_regmap_gate_data){
1088 .data = &(struct clk_regmap_div_data){
1090 .shift = 4,
1105 .data = &(struct clk_regmap_div_data){
1107 .shift = 12,
1122 .data = &(struct clk_regmap_mux_data){
1125 .shift = 8,
1141 .data = &(struct clk_regmap_div_data){
1143 .shift = 0,
1168 .data = &(struct clk_regmap_mux_data){
1171 .shift = 16,
1183 .data = &(struct clk_regmap_gate_data){
1199 .data = &(struct clk_regmap_gate_data){
1215 .data = &(struct clk_regmap_gate_data){
1245 .data = &(struct clk_regmap_gate_data){
1275 .data = &(struct clk_regmap_gate_data){
1305 .data = &(struct clk_regmap_gate_data){
1335 .data = &(struct clk_regmap_gate_data){
1351 .data = &(struct clk_regmap_mux_data){
1354 .shift = 16,
1366 .data = &(struct clk_regmap_gate_data){
1382 .data = &(struct clk_regmap_gate_data){
1398 .data = &(struct clk_regmap_gate_data){
1428 .data = &(struct clk_regmap_gate_data){
1458 .data = &(struct clk_regmap_gate_data){
1488 .data = &(struct clk_regmap_gate_data){
1518 .data = &(struct clk_regmap_gate_data){
1542 .data = &(struct clk_regmap_mux_data){
1545 .shift = 20,
1557 .data = &(struct clk_regmap_gate_data){
1573 .data = &(struct clk_regmap_mux_data){
1576 .shift = 24,
1588 .data = &(struct clk_regmap_gate_data){
1604 .data = &(struct clk_regmap_mux_data){
1607 .shift = 28,
1619 .data = &(struct clk_regmap_gate_data){
1635 .data = &(struct clk_regmap_mux_data){
1638 .shift = 16,
1650 .data = &(struct clk_regmap_gate_data){
1674 .data = &(struct clk_regmap_mux_data){
1677 .shift = 12,
1689 .data = &(struct clk_regmap_gate_data){
1705 .data = &(struct clk_regmap_mux_data){
1708 .shift = 28,
1720 .data = &(struct clk_regmap_gate_data){
1736 .data = &(struct clk_regmap_mux_data){
1739 .shift = 9,
1749 .index = -1,
1757 .data = &(struct clk_regmap_div_data){
1759 .shift = 0,
1774 .data = &(struct clk_regmap_gate_data){
1791 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1792 * actually manage this glitch-free mux because it does top-to-bottom
1795 * Meson8 only has mali_0 and no glitch-free mux.
1798 { .fw_name = "xtal", .name = "xtal", .index = -1, },
1810 .data = &(struct clk_regmap_mux_data){
1813 .shift = 9,
1832 .data = &(struct clk_regmap_div_data){
1834 .shift = 0,
1849 .data = &(struct clk_regmap_gate_data){
1865 .data = &(struct clk_regmap_mux_data){
1868 .shift = 25,
1887 .data = &(struct clk_regmap_div_data){
1889 .shift = 16,
1904 .data = &(struct clk_regmap_gate_data){
1920 .data = &(struct clk_regmap_mux_data){
1923 .shift = 31,
1950 .data = &(struct meson_clk_pll_data){
1953 .shift = 30,
1958 .shift = 0,
1963 .shift = 9,
1968 .shift = 31,
1973 .shift = 29,
1986 .index = -1,
1993 .data = &(struct clk_regmap_div_data){
1995 .shift = 16,
2025 .data = &(struct clk_regmap_mux_data){
2028 .shift = 9,
2040 .data = &(struct clk_regmap_mux_data){
2043 .shift = 9,
2055 .data = &(struct clk_regmap_div_data){
2057 .shift = 0,
2072 .index = -1,
2080 .data = &(struct clk_regmap_gate_data){
2096 .data = &(struct clk_regmap_mux_data){
2099 .shift = 25,
2111 .data = &(struct clk_regmap_mux_data){
2114 .shift = 25,
2126 .data = &(struct clk_regmap_div_data){
2128 .shift = 16,
2143 .index = -1,
2151 .data = &(struct clk_regmap_gate_data){
2168 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2169 * actually manage this glitch-free mux because it does top-to-bottom
2172 * Meson8 only has vpu_0 and no glitch-free mux.
2175 .data = &(struct clk_regmap_mux_data){
2178 .shift = 31,
2202 .data = &(struct clk_regmap_mux_data){
2205 .shift = 9,
2218 .data = &(struct clk_regmap_div_data){
2220 .shift = 0,
2236 .data = &(struct clk_regmap_gate_data){
2252 .data = &(struct clk_regmap_div_data){
2254 .shift = 0,
2270 .data = &(struct clk_regmap_gate_data){
2286 .data = &(struct clk_regmap_mux_data){
2289 .shift = 15,
2305 .data = &(struct clk_regmap_mux_data){
2308 .shift = 25,
2321 .data = &(struct clk_regmap_div_data){
2323 .shift = 16,
2339 .data = &(struct clk_regmap_gate_data){
2355 .data = &(struct clk_regmap_mux_data){
2358 .shift = 9,
2371 .data = &(struct clk_regmap_div_data){
2373 .shift = 0,
2389 .data = &(struct clk_regmap_gate_data){
2405 .data = &(struct clk_regmap_mux_data){
2408 .shift = 25,
2421 .data = &(struct clk_regmap_div_data){
2423 .shift = 16,
2439 .data = &(struct clk_regmap_gate_data){
2455 .data = &(struct clk_regmap_mux_data){
2458 .shift = 31,
2483 .data = &(struct clk_regmap_mux_data){
2486 .shift = 9,
2499 .data = &(struct clk_regmap_div_data) {
2501 .shift = 0,
2517 .data = &(struct clk_regmap_gate_data){
2542 .data = &(struct clk_regmap_mux_data){
2545 .shift = 25,
2558 .data = &(struct clk_regmap_div_data){
2560 .shift = 16,
2576 .data = &(struct clk_regmap_gate_data){
2592 .data = &(struct clk_regmap_mux_data){
2595 .shift = 27,
2606 * The parent is specific to origin of the audio data. Let the
3641 return -EINVAL; in meson8b_clk_reset_update()
3645 if (assert != reset->active_low) in meson8b_clk_reset_update()
3646 value = BIT(reset->bit_idx); in meson8b_clk_reset_update()
3650 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, in meson8b_clk_reset_update()
3651 BIT(reset->bit_idx), value); in meson8b_clk_reset_update()
3681 unsigned long event, void *data) in meson8b_cpu_clk_notifier_cb() argument
3691 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); in meson8b_cpu_clk_notifier_cb()
3696 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); in meson8b_cpu_clk_notifier_cb()
3703 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); in meson8b_cpu_clk_notifier_cb()
3727 pr_err("failed to get HHI regmap - Trying obsolete regs\n"); in meson8b_clkc_init_common()
3736 rstc->regmap = map; in meson8b_clkc_init_common()
3737 rstc->reset.ops = &meson8b_clk_reset_ops; in meson8b_clkc_init_common()
3738 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); in meson8b_clkc_init_common()
3739 rstc->reset.of_node = np; in meson8b_clkc_init_common()
3740 ret = reset_controller_register(&rstc->reset); in meson8b_clkc_init_common()
3749 meson8b_clk_regmaps[i]->map = map; in meson8b_clkc_init_common()
3757 if (!clk_hw_onecell_data->hws[i]) in meson8b_clkc_init_common()
3760 ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]); in meson8b_clkc_init_common()
3765 meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK]; in meson8b_clkc_init_common()
3802 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3804 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3806 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",