Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
87 .data = &(struct meson_clk_pll_data){
90 .shift = 30,
95 .shift = 0,
100 .shift = 9,
105 .shift = 0,
110 .shift = 31,
115 .shift = 29,
130 .data = &(struct clk_regmap_div_data){
132 .shift = 16,
164 .data = &(struct meson_clk_pll_data){
167 .shift = 30,
172 .shift = 0,
177 .shift = 9,
182 .shift = 0,
187 .shift = 31,
192 .shift = 28,
212 .data = &(struct meson_clk_pll_data){
215 .shift = 30,
220 .shift = 0,
225 .shift = 9,
229 * On gxl, there is a register shift due to
236 .shift = 0,
241 .shift = 31,
246 .shift = 28,
266 .data = &(struct clk_regmap_div_data){
268 .shift = 16,
284 .data = &(struct clk_regmap_div_data){
286 .shift = 22,
302 .data = &(struct clk_regmap_div_data){
304 .shift = 18,
320 .data = &(struct clk_regmap_div_data){
322 .shift = 21,
338 .data = &(struct clk_regmap_div_data){
340 .shift = 23,
356 .data = &(struct clk_regmap_div_data){
358 .shift = 19,
374 .data = &(struct meson_clk_pll_data){
377 .shift = 30,
382 .shift = 0,
387 .shift = 9,
392 .shift = 31,
397 .shift = 29,
412 .data = &(struct clk_regmap_div_data){
414 .shift = 10,
436 .data = &(struct meson_clk_pll_data){
439 .shift = 30,
444 .shift = 0,
449 .shift = 9,
454 .shift = 31,
459 .shift = 29,
485 .data = &(struct meson_clk_pll_data){
488 .shift = 30,
493 .shift = 0,
498 .shift = 9,
503 .shift = 0,
508 .shift = 31,
513 .shift = 29,
531 .data = &(struct clk_regmap_div_data){
533 .shift = 16,
549 .index = -1,
570 .data = &(struct clk_regmap_gate_data){
597 .data = &(struct clk_regmap_gate_data){
616 * b) CCF has a clock hand-off mechanism to make the sure the
635 .data = &(struct clk_regmap_gate_data){
661 .data = &(struct clk_regmap_gate_data){
687 .data = &(struct clk_regmap_gate_data){
702 .data = &(struct clk_regmap_div_data){
704 .shift = 12,
716 .data = &(struct meson_clk_mpll_data){
719 .shift = 0,
724 .shift = 15,
729 .shift = 16,
745 .data = &(struct clk_regmap_gate_data){
759 .data = &(struct meson_clk_mpll_data){
762 .shift = 0,
767 .shift = 15,
772 .shift = 16,
788 .data = &(struct clk_regmap_gate_data){
802 .data = &(struct meson_clk_mpll_data){
805 .shift = 0,
810 .shift = 15,
815 .shift = 16,
831 .data = &(struct clk_regmap_gate_data){
856 .data = &(struct clk_regmap_mux_data){
859 .shift = 12,
876 .data = &(struct clk_regmap_div_data){
878 .shift = 0,
893 .data = &(struct clk_regmap_gate_data){
909 .data = &(struct clk_regmap_mux_data){
912 .shift = 9,
927 .data = &(struct clk_regmap_div_data){
929 .shift = 0,
944 .data = &(struct clk_regmap_gate_data){
961 * muxed by a glitch-free switch. The CCF can manage this glitch-free
962 * mux because it does top-to-bottom updates the each clock tree and
978 .data = &(struct clk_regmap_mux_data){
981 .shift = 9,
999 .data = &(struct clk_regmap_div_data){
1001 .shift = 0,
1016 .data = &(struct clk_regmap_gate_data){
1032 .data = &(struct clk_regmap_mux_data){
1035 .shift = 25,
1053 .data = &(struct clk_regmap_div_data){
1055 .shift = 16,
1070 .data = &(struct clk_regmap_gate_data){
1091 .data = &(struct clk_regmap_mux_data){
1094 .shift = 31,
1106 .data = &(struct clk_regmap_mux_data){
1109 .shift = 9,
1126 .data = &(struct clk_regmap_div_data) {
1128 .shift = 0,
1144 .data = &(struct clk_regmap_gate_data){
1160 .data = &(struct clk_regmap_mux_data){
1163 .shift = 25,
1180 .data = &(struct clk_regmap_div_data){
1182 .shift = 16,
1198 .data = &(struct clk_regmap_gate_data){
1214 .data = &(struct clk_regmap_mux_data){
1217 .shift = 27,
1228 *The parent is specific to origin of the audio data. Let the
1242 { .name = "cts_slow_oscin", .index = -1 },
1248 .data = &(struct clk_regmap_mux_data){
1251 .shift = 16,
1263 .data = &(struct clk_regmap_div_data){
1265 .shift = 0,
1280 .data = &(struct clk_regmap_gate_data){
1311 .data = &(struct clk_regmap_mux_data){
1314 .shift = 9,
1326 .data = &(struct clk_regmap_div_data){
1328 .shift = 0,
1344 .data = &(struct clk_regmap_gate_data){
1361 .data = &(struct clk_regmap_mux_data){
1364 .shift = 25,
1376 .data = &(struct clk_regmap_div_data){
1378 .shift = 16,
1394 .data = &(struct clk_regmap_gate_data){
1411 .data = &(struct clk_regmap_mux_data){
1414 .shift = 9,
1426 .data = &(struct clk_regmap_div_data){
1428 .shift = 0,
1444 .data = &(struct clk_regmap_gate_data){
1469 .data = &(struct clk_regmap_mux_data){
1472 .shift = 9,
1488 .data = &(struct clk_regmap_div_data){
1490 .shift = 0,
1503 .data = &(struct clk_regmap_gate_data){
1517 .data = &(struct clk_regmap_mux_data){
1520 .shift = 25,
1536 .data = &(struct clk_regmap_div_data){
1538 .shift = 16,
1551 .data = &(struct clk_regmap_gate_data){
1565 .data = &(struct clk_regmap_mux_data){
1568 .shift = 31,
1596 .data = &(struct clk_regmap_mux_data){
1599 .shift = 9,
1615 .data = &(struct clk_regmap_div_data){
1617 .shift = 0,
1632 .data = &(struct clk_regmap_gate_data){
1648 .data = &(struct clk_regmap_mux_data){
1651 .shift = 25,
1667 .data = &(struct clk_regmap_div_data){
1669 .shift = 16,
1684 .data = &(struct clk_regmap_gate_data){
1700 .data = &(struct clk_regmap_mux_data){
1703 .shift = 31,
1722 .data = &(struct clk_regmap_gate_data){
1738 .data = &(struct meson_vid_pll_div_data){
1741 .shift = 0,
1746 .shift = 16,
1762 .index = -1,
1778 { .name = "hdmi_pll", .index = -1 },
1782 .data = &(struct clk_regmap_mux_data){
1785 .shift = 18,
1801 .data = &(struct clk_regmap_gate_data){
1827 .data = &(struct clk_regmap_mux_data){
1830 .shift = 16,
1847 .data = &(struct clk_regmap_mux_data){
1850 .shift = 16,
1867 .data = &(struct clk_regmap_gate_data){
1881 .data = &(struct clk_regmap_gate_data){
1895 .data = &(struct clk_regmap_div_data){
1897 .shift = 0,
1912 .data = &(struct clk_regmap_div_data){
1914 .shift = 0,
1929 .data = &(struct clk_regmap_gate_data){
1943 .data = &(struct clk_regmap_gate_data){
1957 .data = &(struct clk_regmap_gate_data){
1971 .data = &(struct clk_regmap_gate_data){
1985 .data = &(struct clk_regmap_gate_data){
1999 .data = &(struct clk_regmap_gate_data){
2013 .data = &(struct clk_regmap_gate_data){
2027 .data = &(struct clk_regmap_gate_data){
2041 .data = &(struct clk_regmap_gate_data){
2055 .data = &(struct clk_regmap_gate_data){
2069 .data = &(struct clk_regmap_gate_data){
2083 .data = &(struct clk_regmap_gate_data){
2215 .data = &(struct clk_regmap_mux_data){
2218 .shift = 28,
2231 .data = &(struct clk_regmap_mux_data){
2234 .shift = 20,
2247 .data = &(struct clk_regmap_mux_data){
2250 .shift = 28,
2278 .data = &(struct clk_regmap_mux_data){
2281 .shift = 16,
2300 .data = &(struct clk_regmap_gate_data){
2316 .data = &(struct clk_regmap_gate_data){
2332 .data = &(struct clk_regmap_gate_data){
2348 .data = &(struct clk_regmap_gate_data){
2373 .data = &(struct clk_regmap_mux_data){
2376 .shift = 9,
2389 .data = &(struct clk_regmap_div_data){
2391 .shift = 0,
2404 .data = &(struct clk_regmap_gate_data){
2427 .data = &(struct clk_regmap_mux_data){
2430 .shift = 9,
2443 .data = &(struct clk_regmap_div_data){
2445 .shift = 0,
2461 .data = &(struct clk_regmap_gate_data){
2477 .data = &(struct clk_regmap_mux_data){
2480 .shift = 25,
2493 .data = &(struct clk_regmap_div_data){
2495 .shift = 16,
2511 .data = &(struct clk_regmap_gate_data){
2543 .data = &(struct clk_regmap_mux_data){
2546 .shift = 12,
2564 .data = &(struct clk_regmap_div_data){
2566 .shift = 0,
2581 .data = &(struct clk_regmap_gate_data){
3519 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3520 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3528 .name = "gxbb-clkc",