33  * a divider in the PLL feedback loop which consists of 7 bits for the integer
58 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_is_prepared()  local
60 	return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;  in mtk_pll_is_prepared()
63 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,  in __mtk_pll_recalc_rate()  argument
66 	int pcwbits = pll->data->pcwbits;  in __mtk_pll_recalc_rate()
72 	/* The fractional part of the PLL divider. */  in __mtk_pll_recalc_rate()
73 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in __mtk_pll_recalc_rate()
90 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_enable()  argument
94 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_enable()
95 		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_enable()
96 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_enable()
97 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_enable()
98 		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;  in __mtk_pll_tuner_enable()
99 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_enable()
103 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_disable()  argument
107 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_disable()
108 		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_disable()
109 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_disable()
110 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_disable()
111 		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;  in __mtk_pll_tuner_disable()
112 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_disable()
116 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,  in mtk_pll_set_rate_regs()  argument
122 	__mtk_pll_tuner_disable(pll);  in mtk_pll_set_rate_regs()
125 	val = readl(pll->pd_addr);  in mtk_pll_set_rate_regs()
126 	val &= ~(POSTDIV_MASK << pll->data->pd_shift);  in mtk_pll_set_rate_regs()
127 	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;  in mtk_pll_set_rate_regs()
130 	if (pll->pd_addr != pll->pcw_addr) {  in mtk_pll_set_rate_regs()
131 		writel(val, pll->pd_addr);  in mtk_pll_set_rate_regs()
132 		val = readl(pll->pcw_addr);  in mtk_pll_set_rate_regs()
136 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,  in mtk_pll_set_rate_regs()
137 			pll->data->pcw_shift);  in mtk_pll_set_rate_regs()
138 	val |= pcw << pll->data->pcw_shift;  in mtk_pll_set_rate_regs()
139 	writel(val, pll->pcw_addr);  in mtk_pll_set_rate_regs()
140 	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;  in mtk_pll_set_rate_regs()
141 	writel(chg, pll->pcw_chg_addr);  in mtk_pll_set_rate_regs()
142 	if (pll->tuner_addr)  in mtk_pll_set_rate_regs()
143 		writel(val + 1, pll->tuner_addr);  in mtk_pll_set_rate_regs()
146 	__mtk_pll_tuner_enable(pll);  in mtk_pll_set_rate_regs()
153  * @pll:	The pll
160 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,  in mtk_pll_calc_values()  argument
163 	unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);  in mtk_pll_calc_values()
164 	const struct mtk_pll_div_table *div_table = pll->data->div_table;  in mtk_pll_calc_values()
169 	if (freq > pll->data->fmax)  in mtk_pll_calc_values()
170 		freq = pll->data->fmax;  in mtk_pll_calc_values()
190 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in mtk_pll_calc_values()
191 	_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);  in mtk_pll_calc_values()
200 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_set_rate()  local
204 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);  in mtk_pll_set_rate()
205 	mtk_pll_set_rate_regs(pll, pcw, postdiv);  in mtk_pll_set_rate()
213 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_recalc_rate()  local
217 	postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;  in mtk_pll_recalc_rate()
220 	pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;  in mtk_pll_recalc_rate()
221 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);  in mtk_pll_recalc_rate()
223 	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);  in mtk_pll_recalc_rate()
229 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_round_rate()  local
233 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);  in mtk_pll_round_rate()
235 	return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);  in mtk_pll_round_rate()
240 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_prepare()  local
244 	r = readl(pll->pwr_addr) | CON0_PWR_ON;  in mtk_pll_prepare()
245 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
248 	r = readl(pll->pwr_addr) & ~CON0_ISO_EN;  in mtk_pll_prepare()
249 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
252 	r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);  in mtk_pll_prepare()
253 	writel(r, pll->en_addr);  in mtk_pll_prepare()
255 	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;  in mtk_pll_prepare()
257 		r = readl(pll->base_addr + REG_CON0) | div_en_mask;  in mtk_pll_prepare()
258 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
261 	__mtk_pll_tuner_enable(pll);  in mtk_pll_prepare()
265 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_prepare()
266 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
267 		r |= pll->data->rst_bar_mask;  in mtk_pll_prepare()
268 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
276 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_unprepare()  local
280 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_unprepare()
281 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
282 		r &= ~pll->data->rst_bar_mask;  in mtk_pll_unprepare()
283 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
286 	__mtk_pll_tuner_disable(pll);  in mtk_pll_unprepare()
288 	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;  in mtk_pll_unprepare()
290 		r = readl(pll->base_addr + REG_CON0) & ~div_en_mask;  in mtk_pll_unprepare()
291 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
294 	r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);  in mtk_pll_unprepare()
295 	writel(r, pll->en_addr);  in mtk_pll_unprepare()
297 	r = readl(pll->pwr_addr) | CON0_ISO_EN;  in mtk_pll_unprepare()
298 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
300 	r = readl(pll->pwr_addr) & ~CON0_PWR_ON;  in mtk_pll_unprepare()
301 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
316 	struct mtk_clk_pll *pll;  in mtk_clk_register_pll()  local
321 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in mtk_clk_register_pll()
322 	if (!pll)  in mtk_clk_register_pll()
325 	pll->base_addr = base + data->reg;  in mtk_clk_register_pll()
326 	pll->pwr_addr = base + data->pwr_reg;  in mtk_clk_register_pll()
327 	pll->pd_addr = base + data->pd_reg;  in mtk_clk_register_pll()
328 	pll->pcw_addr = base + data->pcw_reg;  in mtk_clk_register_pll()
330 		pll->pcw_chg_addr = base + data->pcw_chg_reg;  in mtk_clk_register_pll()
332 		pll->pcw_chg_addr = pll->base_addr + REG_CON1;  in mtk_clk_register_pll()
334 		pll->tuner_addr = base + data->tuner_reg;  in mtk_clk_register_pll()
336 		pll->tuner_en_addr = base + data->tuner_en_reg;  in mtk_clk_register_pll()
338 		pll->en_addr = base + data->en_reg;  in mtk_clk_register_pll()
340 		pll->en_addr = pll->base_addr + REG_CON0;  in mtk_clk_register_pll()
341 	pll->hw.init = &init;  in mtk_clk_register_pll()
342 	pll->data = data;  in mtk_clk_register_pll()
353 	clk = clk_register(NULL, &pll->hw);  in mtk_clk_register_pll()
356 		kfree(pll);  in mtk_clk_register_pll()
375 		const struct mtk_pll_data *pll = &plls[i];  in mtk_clk_register_plls()  local
377 		clk = mtk_clk_register_pll(pll, base);  in mtk_clk_register_plls()
381 					pll->name, PTR_ERR(clk));  in mtk_clk_register_plls()
385 		clk_data->clks[pll->id] = clk;  in mtk_clk_register_plls()