Lines Matching +full:0 +full:x2b0
22 * So we model these clocks' rate as 0, to denote it's not an actual rate.
24 #define DUMMY_RATE 0
484 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
489 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
491 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
493 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
495 0x0040, 24, 3, 31),
498 0x0050, 0, 2, 7),
500 0x0050, 8, 4, 15),
502 0x0050, 16, 3, 23),
504 0x0050, 24, 3, 31),
506 0x0060, 0, 1, 7),
509 0x0060, 8, 3, 15),
511 0x0060, 16, 2, 23),
513 0x0060, 24, 3, 31),
516 0x0070, 0, 3, 7),
518 0x0070, 8, 3, 15),
520 0x0070, 16, 1, 23),
522 0x0070, 24, 3, 31),
525 0x0080, 0, 4, 7),
527 0x0080, 8, 2, 15),
529 0x0080, 16, 3, 23),
531 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
534 0x0090, 0, 3, 7),
536 0x0090, 8, 2, 15),
538 0x0090, 16, 3, 23),
541 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
543 0x00A0, 8, 3, 15),
545 0x00A0, 24, 2, 31),
548 0x00B0, 0, 3, 7),
550 0x00B0, 8, 2, 15),
552 0x00B0, 16, 3, 23),
554 0x00B0, 24, 3, 31),
557 hdmirx_bist_parents, 0x00C0, 0, 3, 7),
559 0x00C0, 8, 2, 15),
561 0x00C0, 16, 2, 23),
563 0x00C0, 24, 3, 31),
566 0x00D0, 0, 2, 7),
568 0x00D0, 16, 2, 23),
570 0x00D0, 24, 3, 31),
573 0x00E0, 0, 1, 7),
575 0x00E0, 8, 3, 15),
577 0x00E0, 16, 4, 23),
580 0x00E0, 24, 3, 31),
582 0x00F0, 0, 3, 7),
584 0x00F0, 8, 2, 15),
586 0x00F0, 16, 1, 23),
589 0x0100, 0, 3),
592 0x012c, 0, 3),
594 0x012c, 3, 3),
596 0x012c, 6, 3),
598 0x012c, 15, 1, 23),
600 0x012c, 16, 1, 24),
602 0x012c, 17, 1, 25),
604 0x012c, 18, 1, 26),
606 0x012c, 19, 1, 27),
608 0x012c, 20, 1, 28),
613 0x0120, 0, 8),
615 0x0120, 8, 8),
617 0x0120, 16, 8),
619 0x0120, 24, 8),
621 0x0124, 0, 8),
623 0x0124, 8, 8),
625 0x0124, 16, 8),
627 0x0124, 24, 8),
629 0x0128, 0, 8),
631 0x0128, 8, 8),
635 .sta_ofs = 0x012C,
671 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mtk_topckgen_init()
698 .set_ofs = 0x0040,
699 .clr_ofs = 0x0044,
700 .sta_ofs = 0x0048,
713 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
746 for (i = 0; i < CLK_INFRA_NR; i++) in mtk_infrasys_init_early()
772 for (i = 0; i < CLK_INFRA_NR; i++) { in mtk_infrasys_init()
787 mtk_register_reset_controller(node, 2, 0x30); in mtk_infrasys_init()
789 return 0; in mtk_infrasys_init()
793 .set_ofs = 0x0008,
794 .clr_ofs = 0x0010,
795 .sta_ofs = 0x0018,
799 .set_ofs = 0x000c,
800 .clr_ofs = 0x0014,
801 .sta_ofs = 0x001c,
854 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
867 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
877 0x40c, 0, 1),
879 0x40c, 1, 1),
881 0x40c, 2, 1),
883 0x40c, 3, 1),
892 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mtk_pericfg_init()
910 mtk_register_reset_controller(node, 2, 0x0); in mtk_pericfg_init()
912 return 0; in mtk_pericfg_init()
937 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
938 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
939 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
940 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
941 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
942 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
943 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
944 21, 0x230, 4, 0x0, 0x234, 0),
945 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
946 21, 0x240, 4, 0x0, 0x244, 0),
947 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
948 21, 0x250, 4, 0x0, 0x254, 0),
949 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
950 31, 0x270, 4, 0x0, 0x274, 0),
951 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
952 31, 0x280, 4, 0x0, 0x284, 0),
953 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
954 31, 0x290, 4, 0x0, 0x294, 0),
955 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
956 31, 0x2a0, 4, 0x0, 0x2a4, 0),
957 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
958 31, 0x2b0, 4, 0x0, 0x2b4, 0),
959 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
960 31, 0x2c0, 4, 0x0, 0x2c4, 0),
961 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
962 21, 0x2d0, 4, 0x0, 0x2d4, 0),