Lines Matching +full:1 +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/x1830-cgu.h>
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled()
93 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
94 -1, -1, -1, -1, -1, -1, -1, 0x4,
95 -1, -1, -1, -1, -1, -1, -1, -1,
96 -1, -1, -1, -1, -1, -1, -1, 0x5,
97 -1, -1, -1, -1, -1, -1, -1, -1,
98 -1, -1, -1, -1, -1, -1, -1, -1,
99 -1, -1, -1, -1, -1, -1, -1, -1,
100 -1, -1, -1, -1, -1, -1, -1, 0x6,
114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
120 .m_offset = 1,
123 .n_offset = 1,
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
143 .m_offset = 1,
146 .n_offset = 1,
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
166 .m_offset = 1,
169 .n_offset = 1,
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
189 .m_offset = 1,
192 .n_offset = 1,
204 /* Custom (SoC-specific) OTG PHY */
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
228 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
229 .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
235 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
236 .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
241 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
243 .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
248 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
254 .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
255 .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
260 .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
261 .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
267 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
269 .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
278 .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
287 .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 },
300 .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
307 .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
317 .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 },
328 .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 },
329 .mux = { CGU_REG_SSICDR, 29, 1 },
341 .mux = { CGU_REG_OPCR, 2, 1},
345 /* Gate-only clocks */
349 .parents = { X1830_CLK_AHB2, -1, -1, -1 },
355 .parents = { X1830_CLK_AHB2, -1, -1, -1 },
356 .gate = { CGU_REG_CLKGR0, 1 },
361 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
367 .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
373 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
379 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
385 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
391 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
397 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
403 .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
409 .parents = { X1830_CLK_SSIPLL, -1, -1, -1 },
415 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
421 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
427 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
428 .gate = { CGU_REG_CLKGR1, 1 },
433 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
459 * in the case where the device node is compatible with "simple-mfd".
461 CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init);