Lines Matching +full:i2c +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/jz4740-cgu.h>
51 0x0, 0x1, -1, 0x3,
71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
98 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
105 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
107 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
114 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
116 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
123 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
125 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
132 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
134 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
141 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
143 CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0,
146 .gate = { CGU_REG_CLKGR, 10 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
152 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
157 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
159 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
160 .gate = { CGU_REG_CLKGR, 6 },
165 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
167 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
168 .gate = { CGU_REG_CLKGR, 4 },
173 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
174 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
175 .gate = { CGU_REG_CLKGR, 7 },
180 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
181 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
182 .gate = { CGU_REG_CLKGR, 14 },
187 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
189 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
190 .gate = { CGU_REG_SCR, 6, true },
193 /* Gate-only clocks */
197 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
198 .gate = { CGU_REG_CLKGR, 0 },
203 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
204 .gate = { CGU_REG_CLKGR, 15 },
209 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
210 .gate = { CGU_REG_CLKGR, 12 },
215 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
216 .gate = { CGU_REG_CLKGR, 13 },
221 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
222 .gate = { CGU_REG_CLKGR, 8 },
226 "i2c", CGU_CLK_GATE,
227 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
228 .gate = { CGU_REG_CLKGR, 3 },
233 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
234 .gate = { CGU_REG_CLKGR, 5 },
239 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
240 .gate = { CGU_REG_CLKGR, 1 },
261 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);