65 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \  argument
66 	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
68 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \  argument
70 	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
73 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \  argument
74 	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
76 #define imx_clk_pfd(name, parent_name, reg, idx) \  argument
77 	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
127 #define imx_clk_frac_pll(name, parent_name, base) \  argument
128 	to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
135 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
138 #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \  argument
139 	to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
142 				const char *parent_name, void __iomem *base,
151 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
175 		const char *parent_name, void __iomem *base, u32 div_mask);
194 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
198 		const char *parent_name, unsigned long flags,
215 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
218 struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
221 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
250 static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,  in imx_clk_hw_pll14xx()  argument
254 	return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk);  in imx_clk_hw_pll14xx()
529 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
597 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,