1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42  * struct clk_scu - Description of one SCU clock
44  * @rsrc_id: resource ID of this SCU clock
60  * struct clk_gpr_scu - Description of one SCU GPR clock
62  * @rsrc_id: resource ID of this SCU clock
63  * @gpr_id: GPR ID index to control the divider
76  * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
77  * @hdr: SCU protocol header
82  * This structure describes the SCU protocol of clock rate set
101  * struct imx_sc_msg_get_clock_rate - clock get rate protocol
102  * @hdr: SCU protocol header
106  * This structure describes the SCU protocol of clock rate get
117  * struct imx_sc_msg_get_clock_parent - clock get parent protocol
118  * @hdr: SCU protocol header
122  * This structure describes the SCU protocol of clock get parent
138  * struct imx_sc_msg_set_clock_parent - clock set parent protocol
139  * @hdr: SCU protocol header
142  * This structure describes the SCU protocol of clock set parent
152  * struct imx_sc_msg_req_clock_enable - clock gate protocol
153  * @hdr: SCU protocol header
159  * This structure describes the SCU protocol of clock gate
176 	return *(u32 *)rsrc - *(u32 *)rsrc_p;  in imx_scu_clk_search_cmp()
186 	p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,  in imx_scu_clk_is_valid()
187 		    sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);  in imx_scu_clk_is_valid()
202 	of_property_read_u32(np, "#clock-cells", &clk_cells);  in imx_clk_scu_init()
209 		pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");  in imx_clk_scu_init()
211 			return -EINVAL;  in imx_clk_scu_init()
220  * clk_scu_recalc_rate - Get clock rate for a SCU clock
224  * Gets the current clock rate of a SCU clock. Returns the current
235 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_recalc_rate()
236 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_recalc_rate()
237 	hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;  in clk_scu_recalc_rate()
238 	hdr->size = 2;  in clk_scu_recalc_rate()
240 	msg.data.req.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_recalc_rate()
241 	msg.data.req.clk = clk->clk_type;  in clk_scu_recalc_rate()
254  * clk_scu_round_rate - Round clock rate for a SCU clock
265 	 * Assume we support all the requested rate and let the SCU firmware  in clk_scu_round_rate()
278 	if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)  in clk_scu_atf_set_cpu_rate()
280 	else if (clk->rsrc_id == IMX_SC_R_A72)  in clk_scu_atf_set_cpu_rate()
283 		return -EINVAL;  in clk_scu_atf_set_cpu_rate()
285 	/* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */  in clk_scu_atf_set_cpu_rate()
293  * clk_scu_set_rate - Set rate for a SCU clock
296  * @parent_rate: rate of the clock parent, not used for SCU clocks
298  * Sets a clock frequency for a SCU clock. Returns the SCU
308 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_set_rate()
309 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_set_rate()
310 	hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;  in clk_scu_set_rate()
311 	hdr->size = 3;  in clk_scu_set_rate()
314 	msg.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_set_rate()
315 	msg.clk = clk->clk_type;  in clk_scu_set_rate()
327 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_get_parent()
328 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_get_parent()
329 	hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;  in clk_scu_get_parent()
330 	hdr->size = 2;  in clk_scu_get_parent()
332 	msg.data.req.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_get_parent()
333 	msg.data.req.clk = clk->clk_type;  in clk_scu_get_parent()
342 	clk->parent_index = msg.data.resp.parent;  in clk_scu_get_parent()
347 static int clk_scu_set_parent(struct clk_hw *hw, u8 index)  in clk_scu_set_parent()  argument
354 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_set_parent()
355 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_set_parent()
356 	hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;  in clk_scu_set_parent()
357 	hdr->size = 2;  in clk_scu_set_parent()
359 	msg.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_set_parent()
360 	msg.clk = clk->clk_type;  in clk_scu_set_parent()
361 	msg.parent = index;  in clk_scu_set_parent()
370 	clk->parent_index = index;  in clk_scu_set_parent()
381 	hdr->ver = IMX_SC_RPC_VERSION;  in sc_pm_clock_enable()
382 	hdr->svc = IMX_SC_RPC_SVC_PM;  in sc_pm_clock_enable()
383 	hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;  in sc_pm_clock_enable()
384 	hdr->size = 3;  in sc_pm_clock_enable()
395  * clk_scu_prepare - Enable a SCU clock
404 	return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,  in clk_scu_prepare()
405 				  clk->clk_type, true, false);  in clk_scu_prepare()
409  * clk_scu_unprepare - Disable a SCU clock
419 	ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,  in clk_scu_unprepare()
420 				 clk->clk_type, false, false);  in clk_scu_unprepare()
461 		return ERR_PTR(-ENOMEM);  in __imx_clk_scu()
463 	clk->rsrc_id = rsrc_id;  in __imx_clk_scu()
464 	clk->clk_type = clk_type;  in __imx_clk_scu()
485 	clk->hw.init = &init;  in __imx_clk_scu()
487 	hw = &clk->hw;  in __imx_clk_scu()
504 	unsigned int rsrc = clkspec->args[0];  in imx_scu_of_clk_src_get()
505 	unsigned int idx = clkspec->args[1];  in imx_scu_of_clk_src_get()
510 		if (clk->clk_type == idx)  in imx_scu_of_clk_src_get()
511 			return clk->hw;  in imx_scu_of_clk_src_get()
514 	return ERR_PTR(-ENODEV);  in imx_scu_of_clk_src_get()
519 	struct device *dev = &pdev->dev;  in imx_clk_scu_probe()
524 	if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||  in imx_clk_scu_probe()
525 	    (clk->rsrc == IMX_SC_R_A72))) {  in imx_clk_scu_probe()
528 		pm_runtime_use_autosuspend(&pdev->dev);  in imx_clk_scu_probe()
539 	hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,  in imx_clk_scu_probe()
540 			   clk->rsrc, clk->clk_type);  in imx_clk_scu_probe()
546 	clk->hw = hw;  in imx_clk_scu_probe()
547 	list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);  in imx_clk_scu_probe()
549 	if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||  in imx_clk_scu_probe()
550 	    (clk->rsrc == IMX_SC_R_A72))) {  in imx_clk_scu_probe()
551 		pm_runtime_mark_last_busy(&pdev->dev);  in imx_clk_scu_probe()
552 		pm_runtime_put_autosuspend(&pdev->dev);  in imx_clk_scu_probe()
555 	dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,  in imx_clk_scu_probe()
556 		clk->clk_type);  in imx_clk_scu_probe()
564 	u32 rsrc_id = clk->rsrc_id;  in imx_clk_scu_suspend()
570 	clk->parent = clk_hw_get_parent(&clk->hw);  in imx_clk_scu_suspend()
572 	/* DC SS needs to handle bypass clock using non-cached clock rate */  in imx_clk_scu_suspend()
573 	if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||  in imx_clk_scu_suspend()
574 		clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||  in imx_clk_scu_suspend()
575 		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||  in imx_clk_scu_suspend()
576 		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)  in imx_clk_scu_suspend()
577 		clk->rate = clk_scu_recalc_rate(&clk->hw, 0);  in imx_clk_scu_suspend()
579 		clk->rate = clk_hw_get_rate(&clk->hw);  in imx_clk_scu_suspend()
580 	clk->is_enabled = clk_hw_is_enabled(&clk->hw);  in imx_clk_scu_suspend()
582 	if (clk->parent)  in imx_clk_scu_suspend()
583 		dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),  in imx_clk_scu_suspend()
584 			clk->parent_index);  in imx_clk_scu_suspend()
586 	if (clk->rate)  in imx_clk_scu_suspend()
587 		dev_dbg(dev, "save rate %d\n", clk->rate);  in imx_clk_scu_suspend()
589 	if (clk->is_enabled)  in imx_clk_scu_suspend()
598 	u32 rsrc_id = clk->rsrc_id;  in imx_clk_scu_resume()
605 	if (clk->parent) {  in imx_clk_scu_resume()
606 		ret = clk_scu_set_parent(&clk->hw, clk->parent_index);  in imx_clk_scu_resume()
608 			clk_hw_get_name(clk->parent),  in imx_clk_scu_resume()
609 			clk->parent_index, !ret ? "success" : "failed");  in imx_clk_scu_resume()
612 	if (clk->rate) {  in imx_clk_scu_resume()
613 		ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);  in imx_clk_scu_resume()
614 		dev_dbg(dev, "restore rate %d %s\n", clk->rate,  in imx_clk_scu_resume()
618 	if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {  in imx_clk_scu_resume()
619 		ret = clk_scu_prepare(&clk->hw);  in imx_clk_scu_resume()
634 		.name = "imx-scu-clk",
671 		return ERR_PTR(-EINVAL);  in imx_clk_scu_alloc_dev()
675 		pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",  in imx_clk_scu_alloc_dev()
677 		return ERR_PTR(-ENOMEM);  in imx_clk_scu_alloc_dev()
686 	pdev->driver_override = "imx-scu-clk";  in imx_clk_scu_alloc_dev()
688 	ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);  in imx_clk_scu_alloc_dev()
706 			clk_hw_unregister(clk->hw);  in imx_clk_scu_unregister()
720 	err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_div_scu_recalc_rate()
721 				      clk->gpr_id, &val);  in clk_gpr_div_scu_recalc_rate()
747 	err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_div_scu_set_rate()
748 				      clk->gpr_id, val);  in clk_gpr_div_scu_set_rate()
750 	return err ? -EINVAL : 0;  in clk_gpr_div_scu_set_rate()
764 	imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_mux_scu_get_parent()
765 				clk->gpr_id, &val);  in clk_gpr_mux_scu_get_parent()
770 static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)  in clk_gpr_mux_scu_set_parent()  argument
774 	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_mux_scu_set_parent()
775 				       clk->gpr_id, index);  in clk_gpr_mux_scu_set_parent()
787 	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_prepare()
788 				       clk->gpr_id, !clk->gate_invert);  in clk_gpr_gate_scu_prepare()
796 	ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_unprepare()
797 				      clk->gpr_id, clk->gate_invert);  in clk_gpr_gate_scu_unprepare()
809 	ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_is_prepared()
810 				      clk->gpr_id, &val);  in clk_gpr_gate_scu_is_prepared()
814 	return clk->gate_invert ? !val : val;  in clk_gpr_gate_scu_is_prepared()
834 		return ERR_PTR(-EINVAL);  in __imx_clk_gpr_scu()
838 		return ERR_PTR(-ENOMEM);  in __imx_clk_gpr_scu()
841 		return ERR_PTR(-EINVAL);  in __imx_clk_gpr_scu()
846 		return ERR_PTR(-ENOMEM);  in __imx_clk_gpr_scu()
849 	clk->rsrc_id = rsrc_id;  in __imx_clk_gpr_scu()
850 	clk->gpr_id = gpr_id;  in __imx_clk_gpr_scu()
851 	clk->flags = flags;  in __imx_clk_gpr_scu()
852 	clk->gate_invert = invert;  in __imx_clk_gpr_scu()
868 	clk->hw.init = &init;  in __imx_clk_gpr_scu()
870 	hw = &clk->hw;  in __imx_clk_gpr_scu()
877 		clk_node->hw = hw;  in __imx_clk_gpr_scu()
878 		clk_node->clk_type = gpr_id;  in __imx_clk_gpr_scu()
879 		list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);  in __imx_clk_gpr_scu()