1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
19 #include "clk-imx8qxp-lpcg.h"
21 #include <dt-bindings/clock/imx8-clock.h>
24  * struct imx8qxp_lpcg_data - Description of one LPCG clock
25  * @id: clock ID
26  * @name: clock name
27  * @parent: parent clock name
28  * @flags: common clock flags
29  * @offset: offset of this LPCG clock
30  * @bit_idx: bit index of this LPCG clock
33  * This structure describes one LPCG clock
46  * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
168 	unsigned int idx = clkspec->args[0] / 4;  in imx_lpcg_of_clk_src_get()
170 	if (idx >= hw_data->num) {  in imx_lpcg_of_clk_src_get()
172 		return ERR_PTR(-EINVAL);  in imx_lpcg_of_clk_src_get()
175 	return hw_data->hws[idx];  in imx_lpcg_of_clk_src_get()
193 	if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))  in imx_lpcg_parse_clks_from_dt()
194 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
197 	base = devm_ioremap_resource(&pdev->dev, res);  in imx_lpcg_parse_clks_from_dt()
201 	count = of_property_count_u32_elems(np, "clock-indices");  in imx_lpcg_parse_clks_from_dt()
203 		dev_err(&pdev->dev, "failed to count clocks\n");  in imx_lpcg_parse_clks_from_dt()
204 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
209 	 * of the count from clock-indices because one LPCG supports up to  in imx_lpcg_parse_clks_from_dt()
210 	 * 8 clock outputs which each of them is fixed to 4 bits. Then we can  in imx_lpcg_parse_clks_from_dt()
211 	 * easily get the clock by clk-indices (bit-offset) / 4.  in imx_lpcg_parse_clks_from_dt()
215 	clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,  in imx_lpcg_parse_clks_from_dt()
218 		return -ENOMEM;  in imx_lpcg_parse_clks_from_dt()
220 	clk_data->num = IMX_LPCG_MAX_CLKS;  in imx_lpcg_parse_clks_from_dt()
221 	clk_hws = clk_data->hws;  in imx_lpcg_parse_clks_from_dt()
223 	ret = of_property_read_u32_array(np, "clock-indices", bit_offset,  in imx_lpcg_parse_clks_from_dt()
226 		dev_err(&pdev->dev, "failed to read clock-indices\n");  in imx_lpcg_parse_clks_from_dt()
227 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
232 		dev_err(&pdev->dev, "failed to get clock parent names\n");  in imx_lpcg_parse_clks_from_dt()
236 	ret = of_property_read_string_array(np, "clock-output-names",  in imx_lpcg_parse_clks_from_dt()
239 		dev_err(&pdev->dev, "failed to read clock-output-names\n");  in imx_lpcg_parse_clks_from_dt()
240 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
243 	pm_runtime_get_noresume(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
244 	pm_runtime_set_active(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
245 	pm_runtime_set_autosuspend_delay(&pdev->dev, 500);  in imx_lpcg_parse_clks_from_dt()
246 	pm_runtime_use_autosuspend(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
247 	pm_runtime_enable(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
252 			dev_warn(&pdev->dev, "invalid bit offset of clock %d\n",  in imx_lpcg_parse_clks_from_dt()
254 			ret = -EINVAL;  in imx_lpcg_parse_clks_from_dt()
258 		clk_hws[idx] = imx_clk_lpcg_scu_dev(&pdev->dev, output_names[i],  in imx_lpcg_parse_clks_from_dt()
262 			dev_warn(&pdev->dev, "failed to register clock %d\n",  in imx_lpcg_parse_clks_from_dt()
269 	ret = devm_of_clk_add_hw_provider(&pdev->dev, imx_lpcg_of_clk_src_get,  in imx_lpcg_parse_clks_from_dt()
274 	pm_runtime_mark_last_busy(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
275 	pm_runtime_put_autosuspend(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
280 	while (--i >= 0) {  in imx_lpcg_parse_clks_from_dt()
286 	pm_runtime_disable(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
293 	struct device *dev = &pdev->dev;  in imx8qxp_lpcg_clk_probe()
294 	struct device_node *np = dev->of_node;  in imx8qxp_lpcg_clk_probe()
311 		return -ENODEV;  in imx8qxp_lpcg_clk_probe()
326 		return -EINVAL;  in imx8qxp_lpcg_clk_probe()
327 	base = devm_ioremap(dev, res->start, resource_size(res));  in imx8qxp_lpcg_clk_probe()
329 		return -ENOMEM;  in imx8qxp_lpcg_clk_probe()
331 	clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,  in imx8qxp_lpcg_clk_probe()
332 				ss_lpcg->num_max), GFP_KERNEL);  in imx8qxp_lpcg_clk_probe()
334 		return -ENOMEM;  in imx8qxp_lpcg_clk_probe()
336 	clk_data->num = ss_lpcg->num_max;  in imx8qxp_lpcg_clk_probe()
337 	clks = clk_data->hws;  in imx8qxp_lpcg_clk_probe()
339 	for (i = 0; i < ss_lpcg->num_lpcg; i++) {  in imx8qxp_lpcg_clk_probe()
340 		lpcg = ss_lpcg->lpcg + i;  in imx8qxp_lpcg_clk_probe()
341 		clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent,  in imx8qxp_lpcg_clk_probe()
342 						  lpcg->flags, base + lpcg->offset,  in imx8qxp_lpcg_clk_probe()
343 						  lpcg->bit_idx, lpcg->hw_gate);  in imx8qxp_lpcg_clk_probe()
346 	for (i = 0; i < clk_data->num; i++) {  in imx8qxp_lpcg_clk_probe()
356 	{ .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
357 	{ .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
358 	{ .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
359 	{ .compatible = "fsl,imx8qxp-lpcg", NULL },
365 		.name = "imx8qxp-lpcg-clk",
376 MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver");