Lines Matching +full:stm32 +full:- +full:timers
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/stm32mp1-clks.h>
163 "ck_hse", "pll4_r", "clk-hse-div2"
375 /* STM32 Composite clock */
388 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
391 cfg->name, in _clk_hw_register_gate()
392 cfg->parent_name, in _clk_hw_register_gate()
393 cfg->flags, in _clk_hw_register_gate()
394 gate_cfg->reg_off + base, in _clk_hw_register_gate()
395 gate_cfg->bit_idx, in _clk_hw_register_gate()
396 gate_cfg->gate_flags, in _clk_hw_register_gate()
406 struct fixed_factor_cfg *ff_cfg = cfg->cfg; in _clk_hw_register_fixed_factor()
408 return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name, in _clk_hw_register_fixed_factor()
409 cfg->flags, ff_cfg->mult, in _clk_hw_register_fixed_factor()
410 ff_cfg->div); in _clk_hw_register_fixed_factor()
419 struct div_cfg *div_cfg = cfg->cfg; in _clk_hw_register_divider_table()
422 cfg->name, in _clk_hw_register_divider_table()
423 cfg->parent_name, in _clk_hw_register_divider_table()
424 cfg->flags, in _clk_hw_register_divider_table()
425 div_cfg->reg_off + base, in _clk_hw_register_divider_table()
426 div_cfg->shift, in _clk_hw_register_divider_table()
427 div_cfg->width, in _clk_hw_register_divider_table()
428 div_cfg->div_flags, in _clk_hw_register_divider_table()
429 div_cfg->table, in _clk_hw_register_divider_table()
439 struct mux_cfg *mux_cfg = cfg->cfg; in _clk_hw_register_mux()
441 return clk_hw_register_mux(dev, cfg->name, cfg->parent_names, in _clk_hw_register_mux()
442 cfg->num_parents, cfg->flags, in _clk_hw_register_mux()
443 mux_cfg->reg_off + base, mux_cfg->shift, in _clk_hw_register_mux()
444 mux_cfg->width, mux_cfg->mux_flags, lock); in _clk_hw_register_mux()
463 spin_lock_irqsave(gate->lock, flags); in mp1_gate_clk_disable()
464 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR); in mp1_gate_clk_disable()
465 spin_unlock_irqrestore(gate->lock, flags); in mp1_gate_clk_disable()
483 if (cfg->mmux) { in _get_stm32_mux()
486 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
488 mmux->mux.reg = cfg->mux->reg_off + base; in _get_stm32_mux()
489 mmux->mux.shift = cfg->mux->shift; in _get_stm32_mux()
490 mmux->mux.mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
491 mmux->mux.flags = cfg->mux->mux_flags; in _get_stm32_mux()
492 mmux->mux.table = cfg->mux->table; in _get_stm32_mux()
493 mmux->mux.lock = lock; in _get_stm32_mux()
494 mmux->mmux = cfg->mmux; in _get_stm32_mux()
495 mux_hw = &mmux->mux.hw; in _get_stm32_mux()
496 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw; in _get_stm32_mux()
501 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
503 mux->reg = cfg->mux->reg_off + base; in _get_stm32_mux()
504 mux->shift = cfg->mux->shift; in _get_stm32_mux()
505 mux->mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
506 mux->flags = cfg->mux->mux_flags; in _get_stm32_mux()
507 mux->table = cfg->mux->table; in _get_stm32_mux()
508 mux->lock = lock; in _get_stm32_mux()
509 mux_hw = &mux->hw; in _get_stm32_mux()
524 return ERR_PTR(-ENOMEM); in _get_stm32_div()
526 div->reg = cfg->div->reg_off + base; in _get_stm32_div()
527 div->shift = cfg->div->shift; in _get_stm32_div()
528 div->width = cfg->div->width; in _get_stm32_div()
529 div->flags = cfg->div->div_flags; in _get_stm32_div()
530 div->table = cfg->div->table; in _get_stm32_div()
531 div->lock = lock; in _get_stm32_div()
533 return &div->hw; in _get_stm32_div()
544 if (cfg->mgate) { in _get_stm32_gate()
547 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
549 mgate->gate.reg = cfg->gate->reg_off + base; in _get_stm32_gate()
550 mgate->gate.bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
551 mgate->gate.flags = cfg->gate->gate_flags; in _get_stm32_gate()
552 mgate->gate.lock = lock; in _get_stm32_gate()
553 mgate->mask = BIT(cfg->mgate->nbr_clk++); in _get_stm32_gate()
555 mgate->mgate = cfg->mgate; in _get_stm32_gate()
557 gate_hw = &mgate->gate.hw; in _get_stm32_gate()
562 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
564 gate->reg = cfg->gate->reg_off + base; in _get_stm32_gate()
565 gate->bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
566 gate->flags = cfg->gate->gate_flags; in _get_stm32_gate()
567 gate->lock = lock; in _get_stm32_gate()
569 gate_hw = &gate->hw; in _get_stm32_gate()
595 if (cfg->ops) in clk_stm32_register_gate_ops()
596 init.ops = cfg->ops; in clk_stm32_register_gate_ops()
600 return ERR_PTR(-ENOMEM); in clk_stm32_register_gate_ops()
602 hw->init = &init; in clk_stm32_register_gate_ops()
628 if (cfg->mux) { in clk_stm32_register_composite()
629 mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock); in clk_stm32_register_composite()
634 if (cfg->mux->ops) in clk_stm32_register_composite()
635 mux_ops = cfg->mux->ops; in clk_stm32_register_composite()
639 if (cfg->div) { in clk_stm32_register_composite()
640 div_hw = _get_stm32_div(dev, base, cfg->div, lock); in clk_stm32_register_composite()
645 if (cfg->div->ops) in clk_stm32_register_composite()
646 div_ops = cfg->div->ops; in clk_stm32_register_composite()
650 if (cfg->gate) { in clk_stm32_register_composite()
651 gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock); in clk_stm32_register_composite()
656 if (cfg->gate->ops) in clk_stm32_register_composite()
657 gate_ops = cfg->gate->ops; in clk_stm32_register_composite()
673 clk_mgate->mgate->flag |= clk_mgate->mask; in mp1_mgate_clk_enable()
685 clk_mgate->mgate->flag &= ~clk_mgate->mask; in mp1_mgate_clk_disable()
687 if (clk_mgate->mgate->flag == 0) in mp1_mgate_clk_disable()
718 for (n = 0; n < clk_mmux->mmux->nbr_clk; n++) in clk_mmux_set_parent()
719 if (clk_mmux->mmux->hws[n] != hw) in clk_mmux_set_parent()
720 clk_hw_reparent(clk_mmux->mmux->hws[n], hwp); in clk_mmux_set_parent()
731 /* STM32 PLL */
759 return readl_relaxed(clk_elem->reg) & PLL_ON; in __pll_is_enabled()
772 spin_lock_irqsave(clk_elem->lock, flags); in pll_enable()
777 reg = readl_relaxed(clk_elem->reg); in pll_enable()
779 writel_relaxed(reg, clk_elem->reg); in pll_enable()
787 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY); in pll_enable()
792 } while (bit_status && --timeout); in pll_enable()
795 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_enable()
806 spin_lock_irqsave(clk_elem->lock, flags); in pll_disable()
808 reg = readl_relaxed(clk_elem->reg); in pll_disable()
810 writel_relaxed(reg, clk_elem->reg); in pll_disable()
812 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_disable()
820 reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET); in pll_frac_val()
835 reg = readl_relaxed(clk_elem->reg + 4); in pll_recalc_rate()
858 spin_lock_irqsave(clk_elem->lock, flags); in pll_is_enabled()
860 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_is_enabled()
868 struct clk_hw *mux_hw = &clk_elem->mux.hw; in pll_get_parent()
898 return ERR_PTR(-ENOMEM); in clk_register_pll()
906 element->mux.lock = lock; in clk_register_pll()
907 element->mux.reg = mux_reg; in clk_register_pll()
908 element->mux.shift = PLL_MUX_SHIFT; in clk_register_pll()
909 element->mux.mask = PLL_MUX_MASK; in clk_register_pll()
910 element->mux.flags = CLK_MUX_READ_ONLY; in clk_register_pll()
911 element->mux.reg = mux_reg; in clk_register_pll()
913 element->hw.init = &init; in clk_register_pll()
914 element->reg = reg; in clk_register_pll()
915 element->lock = lock; in clk_register_pll()
917 hw = &element->hw; in clk_register_pll()
947 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in __bestmult()
975 spin_lock_irqsave(tim_ker->lock, flags); in timer_ker_set_rate()
981 writel_relaxed(0, tim_ker->timpre); in timer_ker_set_rate()
984 writel_relaxed(1, tim_ker->timpre); in timer_ker_set_rate()
987 ret = -EINVAL; in timer_ker_set_rate()
989 spin_unlock_irqrestore(tim_ker->lock, flags); in timer_ker_set_rate()
1001 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in timer_ker_recalc_rate()
1003 timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK; in timer_ker_recalc_rate()
1034 return ERR_PTR(-ENOMEM); in clk_register_cktim()
1042 tim_ker->hw.init = &init; in clk_register_cktim()
1043 tim_ker->lock = lock; in clk_register_cktim()
1044 tim_ker->apbdiv = apbdiv; in clk_register_cktim()
1045 tim_ker->timpre = timpre; in clk_register_cktim()
1047 hw = &tim_ker->hw; in clk_register_cktim()
1079 if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) in clk_divider_rtc_determine_rate()
1082 req->rate = req->best_parent_rate; in clk_divider_rtc_determine_rate()
1103 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; in _clk_register_pll()
1105 return clk_register_pll(dev, cfg->name, cfg->parent_names, in _clk_register_pll()
1106 cfg->num_parents, in _clk_register_pll()
1107 base + stm_pll_cfg->offset, in _clk_register_pll()
1108 base + stm_pll_cfg->muxoff, in _clk_register_pll()
1109 cfg->flags, lock); in _clk_register_pll()
1122 struct stm32_cktim_cfg *cktim_cfg = cfg->cfg; in _clk_register_cktim()
1124 return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags, in _clk_register_cktim()
1125 cktim_cfg->offset_apbdiv + base, in _clk_register_cktim()
1126 cktim_cfg->offset_timpre + base, lock); in _clk_register_cktim()
1136 cfg->name, in _clk_stm32_register_gate()
1137 cfg->parent_name, in _clk_stm32_register_gate()
1138 cfg->flags, in _clk_stm32_register_gate()
1140 cfg->cfg, in _clk_stm32_register_gate()
1150 return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, in _clk_stm32_register_composite()
1151 cfg->num_parents, base, cfg->cfg, in _clk_stm32_register_composite()
1152 cfg->flags, lock); in _clk_stm32_register_composite()
1250 /* STM32 GATE */
1730 GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1732 GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1734 COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1739 GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1740 GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1742 FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1835 /* Kernel Timers */
2099 if (cfg->id == stm32mp1_clock_secured[i]) in stm32_check_security()
2129 .compatible = "st,stm32mp1-rcc",
2133 .compatible = "st,stm32mp1-rcc-secure",
2146 struct clk_hw *hw = ERR_PTR(-ENOENT); in stm32_register_hw_clk()
2148 hws = clk_data->hws; in stm32_register_hw_clk()
2150 if (cfg->func) in stm32_register_hw_clk()
2151 hw = (*cfg->func)(dev, clk_data, base, lock, cfg); in stm32_register_hw_clk()
2154 pr_err("Unable to register %s\n", cfg->name); in stm32_register_hw_clk()
2158 if (cfg->id != NO_ID) in stm32_register_hw_clk()
2159 hws[cfg->id] = hw; in stm32_register_hw_clk()
2188 if (data->clear_offset) { in stm32_reset_update()
2191 addr = data->membase + (bank * reg_width); in stm32_reset_update()
2193 addr += data->clear_offset; in stm32_reset_update()
2201 spin_lock_irqsave(&data->lock, flags); in stm32_reset_update()
2203 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_update()
2210 writel(reg, data->membase + (bank * reg_width)); in stm32_reset_update()
2212 spin_unlock_irqrestore(&data->lock, flags); in stm32_reset_update()
2239 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_status()
2253 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_reset_init()
2256 data = match->data; in stm32_rcc_reset_init()
2260 return -ENOMEM; in stm32_rcc_reset_init()
2262 spin_lock_init(&reset_data->lock); in stm32_rcc_reset_init()
2263 reset_data->membase = base; in stm32_rcc_reset_init()
2264 reset_data->rcdev.owner = THIS_MODULE; in stm32_rcc_reset_init()
2265 reset_data->rcdev.ops = &stm32_reset_ops; in stm32_rcc_reset_init()
2266 reset_data->rcdev.of_node = dev_of_node(dev); in stm32_rcc_reset_init()
2267 reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK; in stm32_rcc_reset_init()
2268 reset_data->clear_offset = data->clear_offset; in stm32_rcc_reset_init()
2270 return reset_controller_register(&reset_data->rcdev); in stm32_rcc_reset_init()
2276 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_clock_init()
2281 max_binding = data->maxbinding; in stm32_rcc_clock_init()
2286 return -ENOMEM; in stm32_rcc_clock_init()
2288 clk_data->num = max_binding; in stm32_rcc_clock_init()
2290 hws = clk_data->hws; in stm32_rcc_clock_init()
2293 hws[n] = ERR_PTR(-ENOENT); in stm32_rcc_clock_init()
2295 for (n = 0; n < data->num; n++) { in stm32_rcc_clock_init()
2296 if (data->check_security && data->check_security(&data->cfg[n])) in stm32_rcc_clock_init()
2300 &data->cfg[n]); in stm32_rcc_clock_init()
2303 data->cfg[n].name, err); in stm32_rcc_clock_init()
2321 return -ENODEV; in stm32_rcc_init()
2349 ret = -ENOMEM; in stm32mp1_rcc_init()
2377 return -ENOMEM; in get_clock_deps()
2384 if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT) in get_clock_deps()
2398 struct device *dev = &pdev->dev; in stm32mp1_rcc_clocks_probe()
2409 struct device *dev = &pdev->dev; in stm32mp1_rcc_clocks_remove()