Lines Matching full:plls
282 * PLLs.
301 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
326 * @plls: SoC PLLs descriptors
333 struct k210_pll plls[K210_PLL_NUM]; member
549 struct k210_pll *pll = &ksc->plls[pllid]; in k210_register_pll()
553 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_pll()
554 { .hw = &ksc->plls[K210_PLL1].hw }, in k210_register_pll()
574 k210_init_pll(ksc->regs, i, &ksc->plls[i]); in k210_register_plls()
652 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_aclk()
826 { .hw = &ksc->plls[K210_PLL0].hw } in k210_register_mux_clk()
848 .hw = &ksc->plls[pllid].hw, in k210_register_pll_child()