1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13  * DOC: basic fixed multiplier and divider clock that cannot gate
15  * Traits of this clock:
16  * prepare - clk_prepare only ensures that parents are prepared
17  * enable - clk_enable only ensures that parents are enabled
18  * rate - rate is fixed.  clk->rate = parent->rate / div * mult
19  * parent - fixed parent.  No clk_set_parent support
28 	rate = (unsigned long long int)parent_rate * fix->mult;  in clk_factor_recalc_rate()
29 	do_div(rate, fix->div);  in clk_factor_recalc_rate()
41 		best_parent = (rate / fix->mult) * fix->div;  in clk_factor_round_rate()
45 	return (*prate / fix->div) * fix->mult;  in clk_factor_round_rate()
76 	clk_hw_unregister(&fix->hw);  in devm_clk_hw_register_fixed_factor_release()
82 		unsigned long flags, unsigned int mult, unsigned int div,  in __clk_hw_register_fixed_factor()  argument
93 		return ERR_PTR(-EINVAL);  in __clk_hw_register_fixed_factor()
101 		return ERR_PTR(-ENOMEM);  in __clk_hw_register_fixed_factor()
104 	fix->mult = mult;  in __clk_hw_register_fixed_factor()
105 	fix->div = div;  in __clk_hw_register_fixed_factor()
106 	fix->hw.init = &init;  in __clk_hw_register_fixed_factor()
117 	hw = &fix->hw;  in __clk_hw_register_fixed_factor()
136 		unsigned int mult, unsigned int div)  in clk_hw_register_fixed_factor()  argument
138 	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,  in clk_hw_register_fixed_factor()
139 					      flags, mult, div, false);  in clk_hw_register_fixed_factor()
145 		unsigned int mult, unsigned int div)  in clk_register_fixed_factor()  argument
150 					  div);  in clk_register_fixed_factor()
153 	return hw->clk;  in clk_register_fixed_factor()
183 		unsigned int mult, unsigned int div)  in devm_clk_hw_register_fixed_factor()  argument
185 	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,  in devm_clk_hw_register_fixed_factor()
186 			flags, mult, div, true);  in devm_clk_hw_register_fixed_factor()
192 	{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
199 	const char *clk_name = node->name;  in _of_fixed_factor_clk_setup()
201 	u32 div, mult;  in _of_fixed_factor_clk_setup()  local
204 	if (of_property_read_u32(node, "clock-div", &div)) {  in _of_fixed_factor_clk_setup()
205 		pr_err("%s Fixed factor clock <%pOFn> must have a clock-div property\n",  in _of_fixed_factor_clk_setup()
207 		return ERR_PTR(-EIO);  in _of_fixed_factor_clk_setup()
210 	if (of_property_read_u32(node, "clock-mult", &mult)) {  in _of_fixed_factor_clk_setup()
211 		pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",  in _of_fixed_factor_clk_setup()
213 		return ERR_PTR(-EIO);  in _of_fixed_factor_clk_setup()
216 	of_property_read_string(node, "clock-output-names", &clk_name);  in _of_fixed_factor_clk_setup()
222 					    flags, mult, div, false);  in _of_fixed_factor_clk_setup()
225 		 * Clear OF_POPULATED flag so that clock registration can be  in _of_fixed_factor_clk_setup()
242  * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
243  * @node:	device node for the clock
249 CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock",
256 	of_clk_del_provider(pdev->dev.of_node);  in of_fixed_factor_clk_remove()
270 	clk = _of_fixed_factor_clk_setup(pdev->dev.of_node);  in of_fixed_factor_clk_probe()
280 	{ .compatible = "fixed-factor-clock" },