54 #define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)  argument
55 #define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)  argument
56 #define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)  argument
57 #define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)  argument
58 #define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)  argument
59 #define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)  argument
61 #define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)  argument
106  * Gating control and status is managed by a 32-bit gate register.
109  * - (no gate)
110  *     A clock with no gate is assumed to be always enabled.
112  *     Enabling or disabling clocks with this type of gate is
115  *     of auto-gated clocks can be read from the gate status bit.
119  *     clearing the enable bit.  The current gate status of a gate
120  *     under software control can be read from the gate status bit.
122  *     status bit can be polled to verify that the gate has entered
127  *     determined by the hw_sw_sel bit of the gate register.
130 	u32 offset;		/* gate register offset */
131 	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
138  * Gate flags:
139  *   HW         means this gate can be auto-gated
140  *   SW         means the state of this gate can be software controlled
141  *   NO_DISABLE means this gate is (only) enabled if under software control
142  *   SW_MANAGED means the status of this gate is under software control
143  *   ENABLED    means this software-managed gate is *supposed* to be enabled
145 #define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
146 #define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
153  * Gate initialization macros.
155  * Any gate initially under software control will be enabled.
158 /* A hardware/software gate initially under software control */
165 		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
166 			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
167 			FLAG(GATE, EXISTS),				\
170 /* A hardware/software gate initially under hardware control */
177 		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
178 			FLAG(GATE, EXISTS),				\
181 /* A hardware-or-enabled gate (enabled if not under hardware control) */
188 		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
189 			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
192 /* A software-only gate */
198 		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
199 			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
202 /* A hardware-only gate */
207 		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
210 /* Gate hysteresis for clocks */
262  * using its gate).  In addition, a trigger register (described
392 	struct bcm_clk_gate gate;  member