40 	struct sam9x60_pll_core core;  member
46 	struct sam9x60_pll_core core;  member
51 #define to_sam9x60_frac(core)	container_of(core, struct sam9x60_frac, core)  argument
52 #define to_sam9x60_div(core)	container_of(core, struct sam9x60_div, core)  argument
71 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_recalc_rate()  local
72 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_recalc_rate()
80 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_prepare()  local
81 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_prepare()
82 	struct regmap *regmap = core->regmap;  in sam9x60_frac_pll_prepare()
86 	spin_lock_irqsave(core->lock, flags);  in sam9x60_frac_pll_prepare()
89 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_frac_pll_prepare()
91 	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;  in sam9x60_frac_pll_prepare()
92 	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;  in sam9x60_frac_pll_prepare()
94 	if (sam9x60_frac_pll_ready(regmap, core->id) &&  in sam9x60_frac_pll_prepare()
99 	if (core->characteristics->upll)  in sam9x60_frac_pll_prepare()
106 		     (frac->mul << core->layout->mul_shift) |  in sam9x60_frac_pll_prepare()
107 		     (frac->frac << core->layout->frac_shift));  in sam9x60_frac_pll_prepare()
109 	if (core->characteristics->upll) {  in sam9x60_frac_pll_prepare()
125 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_prepare()
133 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_prepare()
135 	while (!sam9x60_pll_ready(regmap, core->id))  in sam9x60_frac_pll_prepare()
139 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_frac_pll_prepare()
146 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_unprepare()  local
147 	struct regmap *regmap = core->regmap;  in sam9x60_frac_pll_unprepare()
150 	spin_lock_irqsave(core->lock, flags);  in sam9x60_frac_pll_unprepare()
153 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_frac_pll_unprepare()
157 	if (core->characteristics->upll)  in sam9x60_frac_pll_unprepare()
163 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_unprepare()
165 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_frac_pll_unprepare()
170 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_is_prepared()  local
172 	return sam9x60_pll_ready(core->regmap, core->id);  in sam9x60_frac_pll_is_prepared()
175 static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,  in sam9x60_frac_pll_compute_mul_frac()  argument
180 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_compute_mul_frac()
219 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_round_rate()  local
221 	return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);  in sam9x60_frac_pll_round_rate()
227 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_set_rate()  local
229 	return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);  in sam9x60_frac_pll_set_rate()
235 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_set_rate_chg()  local
236 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_set_rate_chg()
237 	struct regmap *regmap = core->regmap;  in sam9x60_frac_pll_set_rate_chg()
242 	ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);  in sam9x60_frac_pll_set_rate_chg()
246 	spin_lock_irqsave(core->lock, irqflags);  in sam9x60_frac_pll_set_rate_chg()
249 			   core->id);  in sam9x60_frac_pll_set_rate_chg()
251 	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;  in sam9x60_frac_pll_set_rate_chg()
252 	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;  in sam9x60_frac_pll_set_rate_chg()
258 		     (frac->mul << core->layout->mul_shift) |  in sam9x60_frac_pll_set_rate_chg()
259 		     (frac->frac << core->layout->frac_shift));  in sam9x60_frac_pll_set_rate_chg()
263 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set_rate_chg()
272 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set_rate_chg()
274 	while (!sam9x60_pll_ready(regmap, core->id))  in sam9x60_frac_pll_set_rate_chg()
278 	spin_unlock_irqrestore(core->lock, irqflags);  in sam9x60_frac_pll_set_rate_chg()
303 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_prepare()  local
304 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_prepare()
305 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_prepare()
309 	spin_lock_irqsave(core->lock, flags);  in sam9x60_div_pll_prepare()
311 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_div_pll_prepare()
313 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_prepare()
316 	if (!!(val & core->layout->endiv_mask) && cdiv == div->div)  in sam9x60_div_pll_prepare()
320 			   core->layout->div_mask | core->layout->endiv_mask,  in sam9x60_div_pll_prepare()
321 			   (div->div << core->layout->div_shift) |  in sam9x60_div_pll_prepare()
322 			   (1 << core->layout->endiv_shift));  in sam9x60_div_pll_prepare()
326 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_div_pll_prepare()
328 	while (!sam9x60_pll_ready(regmap, core->id))  in sam9x60_div_pll_prepare()
332 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_div_pll_prepare()
339 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_unprepare()  local
340 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_unprepare()
343 	spin_lock_irqsave(core->lock, flags);  in sam9x60_div_pll_unprepare()
346 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_div_pll_unprepare()
349 			   core->layout->endiv_mask, 0);  in sam9x60_div_pll_unprepare()
353 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_div_pll_unprepare()
355 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_div_pll_unprepare()
360 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_is_prepared()  local
361 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_is_prepared()
365 	spin_lock_irqsave(core->lock, flags);  in sam9x60_div_pll_is_prepared()
368 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_div_pll_is_prepared()
371 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_div_pll_is_prepared()
373 	return !!(val & core->layout->endiv_mask);  in sam9x60_div_pll_is_prepared()
379 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_recalc_rate()  local
380 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_recalc_rate()
385 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,  in sam9x60_div_pll_compute_div()  argument
390 							core->characteristics;  in sam9x60_div_pll_compute_div()
391 	struct clk_hw *parent = clk_hw_get_parent(&core->hw);  in sam9x60_div_pll_compute_div()
403 	for (divid = 1; divid < core->layout->div_mask; divid++) {  in sam9x60_div_pll_compute_div()
431 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_round_rate()  local
433 	return sam9x60_div_pll_compute_div(core, parent_rate, rate);  in sam9x60_div_pll_round_rate()
439 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_set_rate()  local
440 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_set_rate()
450 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_set_rate_chg()  local
451 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_set_rate_chg()
452 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_set_rate_chg()
458 	spin_lock_irqsave(core->lock, irqflags);  in sam9x60_div_pll_set_rate_chg()
460 			   core->id);  in sam9x60_div_pll_set_rate_chg()
462 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_set_rate_chg()
469 			   core->layout->div_mask,  in sam9x60_div_pll_set_rate_chg()
470 			   (div->div << core->layout->div_shift));  in sam9x60_div_pll_set_rate_chg()
474 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_div_pll_set_rate_chg()
476 	while (!sam9x60_pll_ready(regmap, core->id))  in sam9x60_div_pll_set_rate_chg()
480 	spin_unlock_irqrestore(core->lock, irqflags);  in sam9x60_div_pll_set_rate_chg()
534 	frac->core.id = id;  in sam9x60_clk_register_frac_pll()
535 	frac->core.hw.init = &init;  in sam9x60_clk_register_frac_pll()
536 	frac->core.characteristics = characteristics;  in sam9x60_clk_register_frac_pll()
537 	frac->core.layout = layout;  in sam9x60_clk_register_frac_pll()
538 	frac->core.regmap = regmap;  in sam9x60_clk_register_frac_pll()
539 	frac->core.lock = lock;  in sam9x60_clk_register_frac_pll()
541 	spin_lock_irqsave(frac->core.lock, irqflags);  in sam9x60_clk_register_frac_pll()
562 		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,  in sam9x60_clk_register_frac_pll()
569 	spin_unlock_irqrestore(frac->core.lock, irqflags);  in sam9x60_clk_register_frac_pll()
571 	hw = &frac->core.hw;  in sam9x60_clk_register_frac_pll()
581 	spin_unlock_irqrestore(frac->core.lock, irqflags);  in sam9x60_clk_register_frac_pll()
615 	div->core.id = id;  in sam9x60_clk_register_div_pll()
616 	div->core.hw.init = &init;  in sam9x60_clk_register_div_pll()
617 	div->core.characteristics = characteristics;  in sam9x60_clk_register_div_pll()
618 	div->core.layout = layout;  in sam9x60_clk_register_div_pll()
619 	div->core.regmap = regmap;  in sam9x60_clk_register_div_pll()
620 	div->core.lock = lock;  in sam9x60_clk_register_div_pll()
622 	spin_lock_irqsave(div->core.lock, irqflags);  in sam9x60_clk_register_div_pll()
629 	spin_unlock_irqrestore(div->core.lock, irqflags);  in sam9x60_clk_register_div_pll()
631 	hw = &div->core.hw;  in sam9x60_clk_register_div_pll()