48 static inline bool clk_master_ready(struct clk_master *master)  in clk_master_ready()  argument
50 	unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;  in clk_master_ready()
53 	regmap_read(master->regmap, AT91_PMC_SR, &status);  in clk_master_ready()
60 	struct clk_master *master = to_clk_master(hw);  in clk_master_prepare()  local
63 	spin_lock_irqsave(master->lock, flags);  in clk_master_prepare()
65 	while (!clk_master_ready(master))  in clk_master_prepare()
68 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_prepare()
75 	struct clk_master *master = to_clk_master(hw);  in clk_master_is_prepared()  local
79 	spin_lock_irqsave(master->lock, flags);  in clk_master_is_prepared()
80 	status = clk_master_ready(master);  in clk_master_is_prepared()
81 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_is_prepared()
91 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_recalc_rate()  local
92 	const struct clk_master_layout *layout = master->layout;  in clk_master_div_recalc_rate()
94 						master->characteristics;  in clk_master_div_recalc_rate()
97 	spin_lock_irqsave(master->lock, flags);  in clk_master_div_recalc_rate()
98 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_div_recalc_rate()
99 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_div_recalc_rate()
108 		pr_warn("master clk div is underclocked");  in clk_master_div_recalc_rate()
110 		pr_warn("master clk div is overclocked");  in clk_master_div_recalc_rate()
124 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_set_rate()  local
126 						master->characteristics;  in clk_master_div_set_rate()
147 	spin_lock_irqsave(master->lock, flags);  in clk_master_div_set_rate()
148 	regmap_update_bits(master->regmap, master->layout->offset,  in clk_master_div_set_rate()
151 	while (!clk_master_ready(master))  in clk_master_div_set_rate()
153 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_div_set_rate()
161 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_determine_rate()  local
163 						master->characteristics;  in clk_master_div_determine_rate()
235 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_determine_rate()  local
238 							master->characteristics;  in clk_master_pres_determine_rate()
244 	if (master->chg_pid < 0)  in clk_master_pres_determine_rate()
247 	parent = clk_hw_get_parent_by_index(hw, master->chg_pid);  in clk_master_pres_determine_rate()
273 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_set_rate()  local
286 	spin_lock_irqsave(master->lock, flags);  in clk_master_pres_set_rate()
287 	regmap_update_bits(master->regmap, master->layout->offset,  in clk_master_pres_set_rate()
288 			   (MASTER_PRES_MASK << master->layout->pres_shift),  in clk_master_pres_set_rate()
289 			   (pres << master->layout->pres_shift));  in clk_master_pres_set_rate()
291 	while (!clk_master_ready(master))  in clk_master_pres_set_rate()
293 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_pres_set_rate()
301 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_recalc_rate()  local
303 						master->characteristics;  in clk_master_pres_recalc_rate()
307 	spin_lock_irqsave(master->lock, flags);  in clk_master_pres_recalc_rate()
308 	regmap_read(master->regmap, master->layout->offset, &val);  in clk_master_pres_recalc_rate()
309 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_pres_recalc_rate()
311 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;  in clk_master_pres_recalc_rate()
322 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_get_parent()  local
326 	spin_lock_irqsave(master->lock, flags);  in clk_master_pres_get_parent()
327 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_pres_get_parent()
328 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_pres_get_parent()
358 	struct clk_master *master;  in at91_clk_register_master_internal()  local
366 	master = kzalloc(sizeof(*master), GFP_KERNEL);  in at91_clk_register_master_internal()
367 	if (!master)  in at91_clk_register_master_internal()
376 	master->hw.init = &init;  in at91_clk_register_master_internal()
377 	master->layout = layout;  in at91_clk_register_master_internal()
378 	master->characteristics = characteristics;  in at91_clk_register_master_internal()
379 	master->regmap = regmap;  in at91_clk_register_master_internal()
380 	master->chg_pid = chg_pid;  in at91_clk_register_master_internal()
381 	master->lock = lock;  in at91_clk_register_master_internal()
383 	hw = &master->hw;  in at91_clk_register_master_internal()
384 	ret = clk_hw_register(NULL, &master->hw);  in at91_clk_register_master_internal()
386 		kfree(master);  in at91_clk_register_master_internal()
438 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_recalc_rate()  local
440 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));  in clk_sama7g5_master_recalc_rate()
446 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_determine_rate()  local
476 	if (master->chg_pid < 0)  in clk_sama7g5_master_determine_rate()
479 	parent = clk_hw_get_parent_by_index(hw, master->chg_pid);  in clk_sama7g5_master_determine_rate()
515 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_get_parent()  local
519 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_get_parent()
520 	index = clk_mux_val_to_index(&master->hw, master->mux_table, 0,  in clk_sama7g5_master_get_parent()
521 				     master->parent);  in clk_sama7g5_master_get_parent()
522 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_get_parent()
529 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_set_parent()  local
535 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_set_parent()
536 	master->parent = clk_mux_index_to_val(master->mux_table, 0, index);  in clk_sama7g5_master_set_parent()
537 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_set_parent()
544 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_enable()  local
548 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_enable()
550 	regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));  in clk_sama7g5_master_enable()
551 	regmap_read(master->regmap, PMC_MCR, &val);  in clk_sama7g5_master_enable()
552 	regmap_update_bits(master->regmap, PMC_MCR,  in clk_sama7g5_master_enable()
555 			   PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) |  in clk_sama7g5_master_enable()
556 			   (master->div << MASTER_DIV_SHIFT) |  in clk_sama7g5_master_enable()
557 			   PMC_MCR_CMD | PMC_MCR_ID(master->id));  in clk_sama7g5_master_enable()
562 	while ((cparent != master->parent) && !clk_master_ready(master))  in clk_sama7g5_master_enable()
565 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_enable()
572 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_disable()  local
575 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_disable()
577 	regmap_write(master->regmap, PMC_MCR, master->id);  in clk_sama7g5_master_disable()
578 	regmap_update_bits(master->regmap, PMC_MCR,  in clk_sama7g5_master_disable()
580 			   PMC_MCR_CMD | PMC_MCR_ID(master->id));  in clk_sama7g5_master_disable()
582 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_disable()
587 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_is_enabled()  local
591 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_is_enabled()
593 	regmap_write(master->regmap, PMC_MCR, master->id);  in clk_sama7g5_master_is_enabled()
594 	regmap_read(master->regmap, PMC_MCR, &val);  in clk_sama7g5_master_is_enabled()
596 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_is_enabled()
604 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_set_rate()  local
616 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_set_rate()
617 	master->div = div;  in clk_sama7g5_master_set_rate()
618 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_set_rate()
642 	struct clk_master *master;  in at91_clk_sama7g5_register_master()  local
653 	master = kzalloc(sizeof(*master), GFP_KERNEL);  in at91_clk_sama7g5_register_master()
654 	if (!master)  in at91_clk_sama7g5_register_master()
667 	master->hw.init = &init;  in at91_clk_sama7g5_register_master()
668 	master->regmap = regmap;  in at91_clk_sama7g5_register_master()
669 	master->id = id;  in at91_clk_sama7g5_register_master()
670 	master->chg_pid = chg_pid;  in at91_clk_sama7g5_register_master()
671 	master->lock = lock;  in at91_clk_sama7g5_register_master()
672 	master->mux_table = mux_table;  in at91_clk_sama7g5_register_master()
674 	spin_lock_irqsave(master->lock, flags);  in at91_clk_sama7g5_register_master()
675 	regmap_write(master->regmap, PMC_MCR, master->id);  in at91_clk_sama7g5_register_master()
676 	regmap_read(master->regmap, PMC_MCR, &val);  in at91_clk_sama7g5_register_master()
677 	master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;  in at91_clk_sama7g5_register_master()
678 	master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;  in at91_clk_sama7g5_register_master()
679 	spin_unlock_irqrestore(master->lock, flags);  in at91_clk_sama7g5_register_master()
681 	hw = &master->hw;  in at91_clk_sama7g5_register_master()
682 	ret = clk_hw_register(NULL, &master->hw);  in at91_clk_sama7g5_register_master()
684 		kfree(master);  in at91_clk_sama7g5_register_master()