90 static void malformed_message(struct xilly_endpoint *endpoint, u32 *buf)  in malformed_message()  argument
101 	dev_warn(endpoint->dev,  in malformed_message()
463 		channel->endpoint = ep;  in xilly_setupchannels()
553 static int xilly_scan_idt(struct xilly_endpoint *endpoint,  in xilly_scan_idt()  argument
557 	unsigned char *idt = endpoint->channels[1]->wr_buffers[0]->addr;  in xilly_scan_idt()
558 	unsigned char *end_of_idt = idt + endpoint->idtlen - 4;  in xilly_scan_idt()
576 		dev_err(endpoint->dev,  in xilly_scan_idt()
582 	len = endpoint->idtlen - (3 + ((int) (scan - idt)));  in xilly_scan_idt()
585 		dev_err(endpoint->dev,  in xilly_scan_idt()
591 	endpoint->num_channels = count;  in xilly_scan_idt()
596 static int xilly_obtain_idt(struct xilly_endpoint *endpoint)  in xilly_obtain_idt()  argument
602 	channel = endpoint->channels[1]; /* This should be generated ad-hoc */  in xilly_obtain_idt()
608 		  endpoint->registers + fpga_buf_ctrl_reg);  in xilly_obtain_idt()
615 		dev_err(endpoint->dev, "Failed to obtain IDT. Aborting.\n");  in xilly_obtain_idt()
617 		if (endpoint->fatal_error)  in xilly_obtain_idt()
623 	endpoint->ephw->hw_sync_sgl_for_cpu(  in xilly_obtain_idt()
624 		channel->endpoint,  in xilly_obtain_idt()
629 	if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) {  in xilly_obtain_idt()
630 		dev_err(endpoint->dev,  in xilly_obtain_idt()
632 			channel->wr_buffers[0]->end_offset, endpoint->idtlen);  in xilly_obtain_idt()
637 		     endpoint->idtlen+1) != 0) {  in xilly_obtain_idt()
638 		dev_err(endpoint->dev, "IDT failed CRC check. Aborting.\n");  in xilly_obtain_idt()
646 		dev_err(endpoint->dev,  in xilly_obtain_idt()
671 	if (channel->endpoint->fatal_error)  in xillybus_read()
738 				channel->endpoint->ephw->hw_sync_sgl_for_cpu(  in xillybus_read()
739 					channel->endpoint,  in xillybus_read()
754 				channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_read()
755 					channel->endpoint,  in xillybus_read()
770 					  channel->endpoint->registers +  in xillybus_read()
852 				mutex_lock(&channel->endpoint->register_mutex);  in xillybus_read()
855 					  channel->endpoint->registers +  in xillybus_read()
861 					  channel->endpoint->registers +  in xillybus_read()
864 				mutex_unlock(&channel->endpoint->  in xillybus_read()
899 			if (channel->endpoint->fatal_error)  in xillybus_read()
928 				if (channel->endpoint->fatal_error)  in xillybus_read()
950 				  channel->endpoint->registers +  in xillybus_read()
965 	if (channel->endpoint->fatal_error)  in xillybus_read()
992 	if (channel->endpoint->fatal_error)  in xillybus_myflush()
1058 		channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_myflush()
1059 			channel->endpoint,  in xillybus_myflush()
1064 		mutex_lock(&channel->endpoint->register_mutex);  in xillybus_myflush()
1067 			  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_myflush()
1072 			  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_myflush()
1074 		mutex_unlock(&channel->endpoint->register_mutex);  in xillybus_myflush()
1123 			dev_warn(channel->endpoint->dev,  in xillybus_myflush()
1139 	if (channel->endpoint->fatal_error)  in xillybus_myflush()
1163 		dev_warn(channel->endpoint->dev,  in xillybus_autoflush()
1166 		dev_err(channel->endpoint->dev,  in xillybus_autoflush()
1184 	if (channel->endpoint->fatal_error)  in xillybus_write()
1278 				channel->endpoint->ephw->hw_sync_sgl_for_cpu(  in xillybus_write()
1279 					channel->endpoint,  in xillybus_write()
1300 				channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_write()
1301 					channel->endpoint,  in xillybus_write()
1306 				mutex_lock(&channel->endpoint->register_mutex);  in xillybus_write()
1309 					  channel->endpoint->registers +  in xillybus_write()
1315 					  channel->endpoint->registers +  in xillybus_write()
1318 				mutex_unlock(&channel->endpoint->  in xillybus_write()
1328 				if (channel->endpoint->fatal_error)  in xillybus_write()
1365 			if (channel->endpoint->fatal_error)  in xillybus_write()
1381 	if (channel->endpoint->fatal_error)  in xillybus_write()
1401 	struct xilly_endpoint *endpoint;  in xillybus_open()  local
1405 	rc = xillybus_find_inode(inode, (void **)&endpoint, &index);  in xillybus_open()
1409 	if (endpoint->fatal_error)  in xillybus_open()
1412 	channel = endpoint->channels[1 + index];  in xillybus_open()
1430 		dev_err(endpoint->dev,  in xillybus_open()
1437 		dev_err(endpoint->dev,  in xillybus_open()
1493 				  channel->endpoint->registers +  in xillybus_open()
1514 				  channel->endpoint->registers +  in xillybus_open()
1542 	if (channel->endpoint->fatal_error)  in xillybus_release()
1558 				  channel->endpoint->registers +  in xillybus_release()
1572 				  channel->endpoint->registers +  in xillybus_release()
1622 					dev_warn(channel->endpoint->dev,  in xillybus_release()
1648 	if (channel->endpoint->fatal_error)  in xillybus_llseek()
1675 	mutex_lock(&channel->endpoint->register_mutex);  in xillybus_llseek()
1678 		  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_llseek()
1682 		  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_llseek()
1684 	mutex_unlock(&channel->endpoint->register_mutex);  in xillybus_llseek()
1715 	poll_wait(filp, &channel->endpoint->ep_wait, wait);  in xillybus_poll()
1758 	if (channel->endpoint->fatal_error)  in xillybus_poll()
1780 	struct xilly_endpoint *endpoint;  in xillybus_init_endpoint()  local
1782 	endpoint = devm_kzalloc(dev, sizeof(*endpoint), GFP_KERNEL);  in xillybus_init_endpoint()
1783 	if (!endpoint)  in xillybus_init_endpoint()
1786 	endpoint->pdev = pdev;  in xillybus_init_endpoint()
1787 	endpoint->dev = dev;  in xillybus_init_endpoint()
1788 	endpoint->ephw = ephw;  in xillybus_init_endpoint()
1789 	endpoint->msg_counter = 0x0b;  in xillybus_init_endpoint()
1790 	endpoint->failed_messages = 0;  in xillybus_init_endpoint()
1791 	endpoint->fatal_error = 0;  in xillybus_init_endpoint()
1793 	init_waitqueue_head(&endpoint->ep_wait);  in xillybus_init_endpoint()
1794 	mutex_init(&endpoint->register_mutex);  in xillybus_init_endpoint()
1796 	return endpoint;  in xillybus_init_endpoint()
1800 static int xilly_quiesce(struct xilly_endpoint *endpoint)  in xilly_quiesce()  argument
1804 	endpoint->idtlen = -1;  in xilly_quiesce()
1806 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xilly_quiesce()
1807 		  endpoint->registers + fpga_dma_control_reg);  in xilly_quiesce()
1809 	t = wait_event_interruptible_timeout(endpoint->ep_wait,  in xilly_quiesce()
1810 					     (endpoint->idtlen >= 0),  in xilly_quiesce()
1813 		dev_err(endpoint->dev,  in xilly_quiesce()
1820 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)  in xillybus_endpoint_discovery()  argument
1827 	struct device *dev = endpoint->dev;  in xillybus_endpoint_discovery()
1846 	iowrite32(1, endpoint->registers + fpga_endian_reg);  in xillybus_endpoint_discovery()
1854 	endpoint->num_channels = 0;  in xillybus_endpoint_discovery()
1856 	rc = xilly_setupchannels(endpoint, bogus_idt, 1);  in xillybus_endpoint_discovery()
1861 	iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg);  in xillybus_endpoint_discovery()
1863 	endpoint->idtlen = -1;  in xillybus_endpoint_discovery()
1869 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xillybus_endpoint_discovery()
1870 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()
1872 	t = wait_event_interruptible_timeout(endpoint->ep_wait,  in xillybus_endpoint_discovery()
1873 					     (endpoint->idtlen >= 0),  in xillybus_endpoint_discovery()
1876 		dev_err(endpoint->dev, "No response from FPGA. Aborting.\n");  in xillybus_endpoint_discovery()
1881 	iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)),  in xillybus_endpoint_discovery()
1882 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()
1885 	while (endpoint->idtlen >= idtbuffersize) {  in xillybus_endpoint_discovery()
1890 	endpoint->num_channels = 1;  in xillybus_endpoint_discovery()
1892 	rc = xilly_setupchannels(endpoint, bogus_idt, 2);  in xillybus_endpoint_discovery()
1896 	rc = xilly_obtain_idt(endpoint);  in xillybus_endpoint_discovery()
1900 	rc = xilly_scan_idt(endpoint, &idt_handle);  in xillybus_endpoint_discovery()
1908 	rc = xilly_setupchannels(endpoint,  in xillybus_endpoint_discovery()
1915 				  endpoint->ephw->owner, endpoint,  in xillybus_endpoint_discovery()
1918 				  endpoint->num_channels,  in xillybus_endpoint_discovery()
1929 	xilly_quiesce(endpoint);  in xillybus_endpoint_discovery()
1936 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint)  in xillybus_endpoint_remove()  argument
1938 	xillybus_cleanup_chrdev(endpoint, endpoint->dev);  in xillybus_endpoint_remove()
1940 	xilly_quiesce(endpoint);  in xillybus_endpoint_remove()