Lines Matching full:channel
102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
120 struct xilly_channel *channel; in xillybus_isr() local
180 channel = ep->channels[msg_channel]; in xillybus_isr()
182 if (msg_dir) { /* Write channel */ in xillybus_isr()
183 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
187 spin_lock(&channel->wr_spinlock); in xillybus_isr()
188 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
190 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
191 channel->wr_empty = 0; in xillybus_isr()
192 channel->wr_sleepy = 0; in xillybus_isr()
193 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
195 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
198 /* Read channel */ in xillybus_isr()
200 if (msg_bufno >= channel->num_rd_buffers) { in xillybus_isr()
205 spin_lock(&channel->rd_spinlock); in xillybus_isr()
206 channel->rd_fpga_buf_idx = msg_bufno; in xillybus_isr()
207 channel->rd_full = 0; in xillybus_isr()
208 spin_unlock(&channel->rd_spinlock); in xillybus_isr()
210 wake_up_interruptible(&channel->rd_wait); in xillybus_isr()
211 if (!channel->rd_synchronous) in xillybus_isr()
214 &channel->rd_workitem, in xillybus_isr()
227 channel = ep->channels[msg_channel]; in xillybus_isr()
229 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
233 spin_lock(&channel->wr_spinlock); in xillybus_isr()
234 if (msg_bufno == channel->wr_host_buf_idx) in xillybus_isr()
235 channel->wr_ready = 1; in xillybus_isr()
236 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
238 wake_up_interruptible(&channel->wr_ready_wait); in xillybus_isr()
253 channel = ep->channels[msg_channel]; in xillybus_isr()
254 spin_lock(&channel->wr_spinlock); in xillybus_isr()
255 channel->wr_eof = msg_bufno; in xillybus_isr()
256 channel->wr_sleepy = 0; in xillybus_isr()
258 channel->wr_hangup = channel->wr_empty && in xillybus_isr()
259 (channel->wr_host_buf_idx == msg_bufno); in xillybus_isr()
261 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
263 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
397 struct xilly_channel *channel; in xilly_setupchannels() local
420 channel = devm_kcalloc(dev, ep->num_channels, in xilly_setupchannels()
422 if (!channel) in xilly_setupchannels()
431 ep->channels[0] = NULL; /* Channel 0 is message buf. */ in xilly_setupchannels()
436 channel->wr_buffers = NULL; in xilly_setupchannels()
437 channel->rd_buffers = NULL; in xilly_setupchannels()
438 channel->num_wr_buffers = 0; in xilly_setupchannels()
439 channel->num_rd_buffers = 0; in xilly_setupchannels()
440 channel->wr_fpga_buf_idx = -1; in xilly_setupchannels()
441 channel->wr_host_buf_idx = 0; in xilly_setupchannels()
442 channel->wr_host_buf_pos = 0; in xilly_setupchannels()
443 channel->wr_empty = 1; in xilly_setupchannels()
444 channel->wr_ready = 0; in xilly_setupchannels()
445 channel->wr_sleepy = 1; in xilly_setupchannels()
446 channel->rd_fpga_buf_idx = 0; in xilly_setupchannels()
447 channel->rd_host_buf_idx = 0; in xilly_setupchannels()
448 channel->rd_host_buf_pos = 0; in xilly_setupchannels()
449 channel->rd_full = 0; in xilly_setupchannels()
450 channel->wr_ref_count = 0; in xilly_setupchannels()
451 channel->rd_ref_count = 0; in xilly_setupchannels()
453 spin_lock_init(&channel->wr_spinlock); in xilly_setupchannels()
454 spin_lock_init(&channel->rd_spinlock); in xilly_setupchannels()
455 mutex_init(&channel->wr_mutex); in xilly_setupchannels()
456 mutex_init(&channel->rd_mutex); in xilly_setupchannels()
457 init_waitqueue_head(&channel->rd_wait); in xilly_setupchannels()
458 init_waitqueue_head(&channel->wr_wait); in xilly_setupchannels()
459 init_waitqueue_head(&channel->wr_ready_wait); in xilly_setupchannels()
461 INIT_DELAYED_WORK(&channel->rd_workitem, xillybus_autoflush); in xilly_setupchannels()
463 channel->endpoint = ep; in xilly_setupchannels()
464 channel->chan_num = i; in xilly_setupchannels()
466 channel->log2_element_size = 0; in xilly_setupchannels()
468 ep->channels[i] = channel++; in xilly_setupchannels()
488 "IDT requests channel out of range. Aborting.\n"); in xilly_setupchannels()
492 channel = ep->channels[channelnum]; /* NULL for msg channel */ in xilly_setupchannels()
495 channel->log2_element_size = ((format > 2) ? in xilly_setupchannels()
499 (1 << channel->log2_element_size); in xilly_setupchannels()
511 channel->num_rd_buffers = bufnum; in xilly_setupchannels()
512 channel->rd_buf_size = bytebufsize; in xilly_setupchannels()
513 channel->rd_allow_partial = allowpartial; in xilly_setupchannels()
514 channel->rd_synchronous = synchronous; in xilly_setupchannels()
515 channel->rd_exclusive_open = exclusive_open; in xilly_setupchannels()
516 channel->seekable = seekable; in xilly_setupchannels()
518 channel->rd_buffers = buffers; in xilly_setupchannels()
522 channel->num_wr_buffers = bufnum; in xilly_setupchannels()
523 channel->wr_buf_size = bytebufsize; in xilly_setupchannels()
525 channel->seekable = seekable; in xilly_setupchannels()
526 channel->wr_supports_nonempty = supports_nonempty; in xilly_setupchannels()
528 channel->wr_allow_partial = allowpartial; in xilly_setupchannels()
529 channel->wr_synchronous = synchronous; in xilly_setupchannels()
530 channel->wr_exclusive_open = exclusive_open; in xilly_setupchannels()
532 channel->wr_buffers = buffers; in xilly_setupchannels()
598 struct xilly_channel *channel; in xilly_obtain_idt() local
602 channel = endpoint->channels[1]; /* This should be generated ad-hoc */ in xilly_obtain_idt()
604 channel->wr_sleepy = 1; in xilly_obtain_idt()
607 (3 << 24), /* Opcode 3 for channel 0 = Send IDT */ in xilly_obtain_idt()
610 t = wait_event_interruptible_timeout(channel->wr_wait, in xilly_obtain_idt()
611 (!channel->wr_sleepy), in xilly_obtain_idt()
624 channel->endpoint, in xilly_obtain_idt()
625 channel->wr_buffers[0]->dma_addr, in xilly_obtain_idt()
626 channel->wr_buf_size, in xilly_obtain_idt()
629 if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) { in xilly_obtain_idt()
632 channel->wr_buffers[0]->end_offset, endpoint->idtlen); in xilly_obtain_idt()
636 if (crc32_le(~0, channel->wr_buffers[0]->addr, in xilly_obtain_idt()
642 version = channel->wr_buffers[0]->addr; in xilly_obtain_idt()
663 struct xilly_channel *channel = filp->private_data; in xillybus_read() local
671 if (channel->endpoint->fatal_error) in xillybus_read()
676 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_read()
683 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_read()
685 empty = channel->wr_empty; in xillybus_read()
686 ready = !empty || channel->wr_ready; in xillybus_read()
689 bufidx = channel->wr_host_buf_idx; in xillybus_read()
690 bufpos = channel->wr_host_buf_pos; in xillybus_read()
691 howmany = ((channel->wr_buffers[bufidx]->end_offset in xillybus_read()
692 + 1) << channel->log2_element_size) in xillybus_read()
700 channel->wr_host_buf_pos += howmany; in xillybus_read()
704 channel->wr_host_buf_pos = 0; in xillybus_read()
706 if (bufidx == channel->wr_fpga_buf_idx) { in xillybus_read()
707 channel->wr_empty = 1; in xillybus_read()
708 channel->wr_sleepy = 1; in xillybus_read()
709 channel->wr_ready = 0; in xillybus_read()
712 if (bufidx >= (channel->num_wr_buffers - 1)) in xillybus_read()
713 channel->wr_host_buf_idx = 0; in xillybus_read()
715 channel->wr_host_buf_idx++; in xillybus_read()
727 reached_eof = channel->wr_empty && in xillybus_read()
728 (channel->wr_host_buf_idx == channel->wr_eof); in xillybus_read()
729 channel->wr_hangup = reached_eof; in xillybus_read()
730 exhausted = channel->wr_empty; in xillybus_read()
731 waiting_bufidx = channel->wr_host_buf_idx; in xillybus_read()
733 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_read()
738 channel->endpoint->ephw->hw_sync_sgl_for_cpu( in xillybus_read()
739 channel->endpoint, in xillybus_read()
740 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
741 channel->wr_buf_size, in xillybus_read()
746 channel->wr_buffers[bufidx]->addr in xillybus_read()
754 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_read()
755 channel->endpoint, in xillybus_read()
756 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
757 channel->wr_buf_size, in xillybus_read()
764 * and the certain channel is protected with in xillybus_read()
765 * the channel-specific mutex. in xillybus_read()
768 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
770 channel->endpoint->registers + in xillybus_read()
775 mutex_unlock(&channel->wr_mutex); in xillybus_read()
789 (channel->wr_synchronous && channel->wr_allow_partial))) in xillybus_read()
819 channel->log2_element_size; in xillybus_read()
820 int buf_elements = channel->wr_buf_size >> in xillybus_read()
821 channel->log2_element_size; in xillybus_read()
828 if (channel->wr_synchronous) { in xillybus_read()
830 if (channel->wr_allow_partial && in xillybus_read()
835 if (!channel->wr_allow_partial && in xillybus_read()
837 (buf_elements * channel->num_wr_buffers))) in xillybus_read()
839 channel->num_wr_buffers - 1; in xillybus_read()
850 if (channel->wr_synchronous || in xillybus_read()
852 mutex_lock(&channel->endpoint->register_mutex); in xillybus_read()
855 channel->endpoint->registers + in xillybus_read()
858 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
861 channel->endpoint->registers + in xillybus_read()
864 mutex_unlock(&channel->endpoint-> in xillybus_read()
875 if (!channel->wr_allow_partial || in xillybus_read()
884 mutex_unlock(&channel->wr_mutex); in xillybus_read()
887 channel->wr_wait, in xillybus_read()
888 (!channel->wr_sleepy))) in xillybus_read()
892 &channel->wr_mutex)) in xillybus_read()
894 } while (channel->wr_sleepy); in xillybus_read()
899 if (channel->endpoint->fatal_error) in xillybus_read()
919 channel->wr_wait, in xillybus_read()
920 (!channel->wr_sleepy), in xillybus_read()
927 mutex_unlock(&channel->wr_mutex); in xillybus_read()
928 if (channel->endpoint->fatal_error) in xillybus_read()
947 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
950 channel->endpoint->registers + in xillybus_read()
963 mutex_unlock(&channel->wr_mutex); in xillybus_read()
965 if (channel->endpoint->fatal_error) in xillybus_read()
981 static int xillybus_myflush(struct xilly_channel *channel, long timeout) in xillybus_myflush() argument
992 if (channel->endpoint->fatal_error) in xillybus_myflush()
994 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_myflush()
999 * Don't flush a closed channel. This can happen when the work queued in xillybus_myflush()
1004 if (!channel->rd_ref_count) in xillybus_myflush()
1007 bufidx = channel->rd_host_buf_idx; in xillybus_myflush()
1010 channel->num_rd_buffers - 1 : in xillybus_myflush()
1013 end_offset_plus1 = channel->rd_host_buf_pos >> in xillybus_myflush()
1014 channel->log2_element_size; in xillybus_myflush()
1016 new_rd_host_buf_pos = channel->rd_host_buf_pos - in xillybus_myflush()
1017 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1021 unsigned char *tail = channel->rd_buffers[bufidx]->addr + in xillybus_myflush()
1022 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1026 channel->rd_leftovers[i] = *tail++; in xillybus_myflush()
1028 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1033 (channel->rd_full || in xillybus_myflush()
1034 (bufidx_minus1 != channel->rd_fpga_buf_idx))) { in xillybus_myflush()
1035 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1045 channel->rd_leftovers[3] = (new_rd_host_buf_pos != 0); in xillybus_myflush()
1049 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_myflush()
1050 channel->rd_full = 1; in xillybus_myflush()
1051 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1053 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_myflush()
1054 channel->rd_host_buf_idx = 0; in xillybus_myflush()
1056 channel->rd_host_buf_idx++; in xillybus_myflush()
1058 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_myflush()
1059 channel->endpoint, in xillybus_myflush()
1060 channel->rd_buffers[bufidx]->dma_addr, in xillybus_myflush()
1061 channel->rd_buf_size, in xillybus_myflush()
1064 mutex_lock(&channel->endpoint->register_mutex); in xillybus_myflush()
1067 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_myflush()
1069 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_myflush()
1072 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_myflush()
1074 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_myflush()
1076 bufidx = channel->num_rd_buffers - 1; in xillybus_myflush()
1081 channel->rd_host_buf_pos = new_rd_host_buf_pos; in xillybus_myflush()
1089 * channel->rd_host_buf_idx the one after it. in xillybus_myflush()
1091 * If bufidx == channel->rd_fpga_buf_idx we're either empty or full. in xillybus_myflush()
1095 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1097 if (bufidx != channel->rd_fpga_buf_idx) in xillybus_myflush()
1098 channel->rd_full = 1; /* in xillybus_myflush()
1103 empty = !channel->rd_full; in xillybus_myflush()
1105 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1116 wait_event_interruptible(channel->rd_wait, in xillybus_myflush()
1117 (!channel->rd_full)); in xillybus_myflush()
1120 channel->rd_wait, in xillybus_myflush()
1121 (!channel->rd_full), in xillybus_myflush()
1123 dev_warn(channel->endpoint->dev, in xillybus_myflush()
1130 if (channel->rd_full) { in xillybus_myflush()
1137 mutex_unlock(&channel->rd_mutex); in xillybus_myflush()
1139 if (channel->endpoint->fatal_error) in xillybus_myflush()
1157 struct xilly_channel *channel = container_of( in xillybus_autoflush() local
1161 rc = xillybus_myflush(channel, -1); in xillybus_autoflush()
1163 dev_warn(channel->endpoint->dev, in xillybus_autoflush()
1166 dev_err(channel->endpoint->dev, in xillybus_autoflush()
1176 struct xilly_channel *channel = filp->private_data; in xillybus_write() local
1184 if (channel->endpoint->fatal_error) in xillybus_write()
1187 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_write()
1194 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_write()
1196 full = channel->rd_full; in xillybus_write()
1199 bufidx = channel->rd_host_buf_idx; in xillybus_write()
1200 bufpos = channel->rd_host_buf_pos; in xillybus_write()
1201 howmany = channel->rd_buf_size - bufpos; in xillybus_write()
1211 ((bufpos >> channel->log2_element_size) == 0))) { in xillybus_write()
1215 channel->rd_host_buf_pos += howmany; in xillybus_write()
1221 channel->rd_buf_size >> in xillybus_write()
1222 channel->log2_element_size; in xillybus_write()
1223 channel->rd_host_buf_pos = 0; in xillybus_write()
1231 channel->log2_element_size; in xillybus_write()
1233 channel->rd_host_buf_pos -= in xillybus_write()
1235 channel->log2_element_size; in xillybus_write()
1237 tail = channel-> in xillybus_write()
1240 channel->log2_element_size); in xillybus_write()
1243 i < channel->rd_host_buf_pos; in xillybus_write()
1245 channel->rd_leftovers[i] = in xillybus_write()
1249 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_write()
1250 channel->rd_full = 1; in xillybus_write()
1252 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_write()
1253 channel->rd_host_buf_idx = 0; in xillybus_write()
1255 channel->rd_host_buf_idx++; in xillybus_write()
1267 exhausted = channel->rd_full; in xillybus_write()
1269 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_write()
1273 channel->rd_buffers[bufidx]->addr; in xillybus_write()
1277 (channel->rd_leftovers[3] != 0)) { in xillybus_write()
1278 channel->endpoint->ephw->hw_sync_sgl_for_cpu( in xillybus_write()
1279 channel->endpoint, in xillybus_write()
1280 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1281 channel->rd_buf_size, in xillybus_write()
1286 *head++ = channel->rd_leftovers[i]; in xillybus_write()
1288 channel->rd_leftovers[3] = 0; /* Clear flag */ in xillybus_write()
1292 channel->rd_buffers[bufidx]->addr + bufpos, in xillybus_write()
1300 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_write()
1301 channel->endpoint, in xillybus_write()
1302 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1303 channel->rd_buf_size, in xillybus_write()
1306 mutex_lock(&channel->endpoint->register_mutex); in xillybus_write()
1309 channel->endpoint->registers + in xillybus_write()
1312 iowrite32((channel->chan_num << 1) | in xillybus_write()
1315 channel->endpoint->registers + in xillybus_write()
1318 mutex_unlock(&channel->endpoint-> in xillybus_write()
1321 channel->rd_leftovers[3] = in xillybus_write()
1322 (channel->rd_host_buf_pos != 0); in xillybus_write()
1326 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1328 if (channel->endpoint->fatal_error) in xillybus_write()
1331 if (!channel->rd_synchronous) in xillybus_write()
1334 &channel->rd_workitem, in xillybus_write()
1347 if ((bytes_done > 0) && channel->rd_allow_partial) in xillybus_write()
1361 if (wait_event_interruptible(channel->rd_wait, in xillybus_write()
1362 (!channel->rd_full))) { in xillybus_write()
1363 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1365 if (channel->endpoint->fatal_error) in xillybus_write()
1374 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1376 if (!channel->rd_synchronous) in xillybus_write()
1378 &channel->rd_workitem, in xillybus_write()
1381 if (channel->endpoint->fatal_error) in xillybus_write()
1387 if ((channel->rd_synchronous) && (bytes_done > 0)) { in xillybus_write()
1402 struct xilly_channel *channel; in xillybus_open() local
1412 channel = endpoint->channels[1 + index]; in xillybus_open()
1413 filp->private_data = channel; in xillybus_open()
1421 if ((filp->f_mode & FMODE_READ) && (!channel->num_wr_buffers)) in xillybus_open()
1424 if ((filp->f_mode & FMODE_WRITE) && (!channel->num_rd_buffers)) in xillybus_open()
1428 (channel->wr_synchronous || !channel->wr_allow_partial || in xillybus_open()
1429 !channel->wr_supports_nonempty)) { in xillybus_open()
1436 (channel->rd_synchronous || !channel->rd_allow_partial)) { in xillybus_open()
1450 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_open()
1456 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_open()
1462 (channel->wr_ref_count != 0) && in xillybus_open()
1463 (channel->wr_exclusive_open)) { in xillybus_open()
1469 (channel->rd_ref_count != 0) && in xillybus_open()
1470 (channel->rd_exclusive_open)) { in xillybus_open()
1476 if (channel->wr_ref_count == 0) { /* First open of file */ in xillybus_open()
1478 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_open()
1479 channel->wr_host_buf_idx = 0; in xillybus_open()
1480 channel->wr_host_buf_pos = 0; in xillybus_open()
1481 channel->wr_fpga_buf_idx = -1; in xillybus_open()
1482 channel->wr_empty = 1; in xillybus_open()
1483 channel->wr_ready = 0; in xillybus_open()
1484 channel->wr_sleepy = 1; in xillybus_open()
1485 channel->wr_eof = -1; in xillybus_open()
1486 channel->wr_hangup = 0; in xillybus_open()
1488 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_open()
1490 iowrite32(1 | (channel->chan_num << 1) | in xillybus_open()
1491 (4 << 24) | /* Opcode 4, open channel */ in xillybus_open()
1492 ((channel->wr_synchronous & 1) << 23), in xillybus_open()
1493 channel->endpoint->registers + in xillybus_open()
1497 channel->wr_ref_count++; in xillybus_open()
1501 if (channel->rd_ref_count == 0) { /* First open of file */ in xillybus_open()
1503 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_open()
1504 channel->rd_host_buf_idx = 0; in xillybus_open()
1505 channel->rd_host_buf_pos = 0; in xillybus_open()
1506 channel->rd_leftovers[3] = 0; /* No leftovers. */ in xillybus_open()
1507 channel->rd_fpga_buf_idx = channel->num_rd_buffers - 1; in xillybus_open()
1508 channel->rd_full = 0; in xillybus_open()
1510 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_open()
1512 iowrite32((channel->chan_num << 1) | in xillybus_open()
1513 (4 << 24), /* Opcode 4, open channel */ in xillybus_open()
1514 channel->endpoint->registers + in xillybus_open()
1518 channel->rd_ref_count++; in xillybus_open()
1523 mutex_unlock(&channel->rd_mutex); in xillybus_open()
1526 mutex_unlock(&channel->wr_mutex); in xillybus_open()
1528 if (!rc && (!channel->seekable)) in xillybus_open()
1537 struct xilly_channel *channel = filp->private_data; in xillybus_release() local
1542 if (channel->endpoint->fatal_error) in xillybus_release()
1546 mutex_lock(&channel->rd_mutex); in xillybus_release()
1548 channel->rd_ref_count--; in xillybus_release()
1550 if (channel->rd_ref_count == 0) { in xillybus_release()
1556 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_release()
1557 (5 << 24), /* Opcode 5, close channel */ in xillybus_release()
1558 channel->endpoint->registers + in xillybus_release()
1561 mutex_unlock(&channel->rd_mutex); in xillybus_release()
1565 mutex_lock(&channel->wr_mutex); in xillybus_release()
1567 channel->wr_ref_count--; in xillybus_release()
1569 if (channel->wr_ref_count == 0) { in xillybus_release()
1570 iowrite32(1 | (channel->chan_num << 1) | in xillybus_release()
1571 (5 << 24), /* Opcode 5, close channel */ in xillybus_release()
1572 channel->endpoint->registers + in xillybus_release()
1578 * the channel or because of a user's EOF), but verify in xillybus_release()
1586 spin_lock_irqsave(&channel->wr_spinlock, in xillybus_release()
1588 buf_idx = channel->wr_fpga_buf_idx; in xillybus_release()
1589 eof = channel->wr_eof; in xillybus_release()
1590 channel->wr_sleepy = 1; in xillybus_release()
1591 spin_unlock_irqrestore(&channel->wr_spinlock, in xillybus_release()
1601 if (buf_idx == channel->num_wr_buffers) in xillybus_release()
1616 channel->wr_wait, in xillybus_release()
1617 (!channel->wr_sleepy))) in xillybus_release()
1620 if (channel->wr_sleepy) { in xillybus_release()
1621 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1622 dev_warn(channel->endpoint->dev, in xillybus_release()
1629 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1637 struct xilly_channel *channel = filp->private_data; in xillybus_llseek() local
1648 if (channel->endpoint->fatal_error) in xillybus_llseek()
1651 mutex_lock(&channel->wr_mutex); in xillybus_llseek()
1652 mutex_lock(&channel->rd_mutex); in xillybus_llseek()
1670 if (pos & ((1 << channel->log2_element_size) - 1)) { in xillybus_llseek()
1675 mutex_lock(&channel->endpoint->register_mutex); in xillybus_llseek()
1677 iowrite32(pos >> channel->log2_element_size, in xillybus_llseek()
1678 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_llseek()
1680 iowrite32((channel->chan_num << 1) | in xillybus_llseek()
1682 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_llseek()
1684 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_llseek()
1687 mutex_unlock(&channel->rd_mutex); in xillybus_llseek()
1688 mutex_unlock(&channel->wr_mutex); in xillybus_llseek()
1696 * Since seekable devices are allowed only when the channel is in xillybus_llseek()
1704 channel->rd_leftovers[3] = 0; in xillybus_llseek()
1711 struct xilly_channel *channel = filp->private_data; in xillybus_poll() local
1715 poll_wait(filp, &channel->endpoint->ep_wait, wait); in xillybus_poll()
1725 if (!channel->wr_synchronous && channel->wr_supports_nonempty) { in xillybus_poll()
1726 poll_wait(filp, &channel->wr_wait, wait); in xillybus_poll()
1727 poll_wait(filp, &channel->wr_ready_wait, wait); in xillybus_poll()
1729 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_poll()
1730 if (!channel->wr_empty || channel->wr_ready) in xillybus_poll()
1733 if (channel->wr_hangup) in xillybus_poll()
1740 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_poll()
1744 * If partial data write is disallowed on a write() channel, in xillybus_poll()
1749 if (channel->rd_allow_partial) { in xillybus_poll()
1750 poll_wait(filp, &channel->rd_wait, wait); in xillybus_poll()
1752 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_poll()
1753 if (!channel->rd_full) in xillybus_poll()
1755 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_poll()
1758 if (channel->endpoint->fatal_error) in xillybus_poll()