1 // SPDX-License-Identifier: GPL-2.0-only
3  * Intel IXP4xx Expansion Bus Controller
51 #define IXP43X_EXP_SYNC_INTEL		BIT(8) /* Only on IXP43x */
52 #define IXP43X_EXP_EXP_CHIP		BIT(7) /* Only on IXP43x */
71 /* Fuses on the IXP43x */
95 		.prop = "intel,ixp4xx-eb-t1",
101 		.prop = "intel,ixp4xx-eb-t2",
107 		.prop = "intel,ixp4xx-eb-t3",
113 		.prop = "intel,ixp4xx-eb-t4",
119 		.prop = "intel,ixp4xx-eb-t5",
125 		.prop = "intel,ixp4xx-eb-byte-access-on-halfword",
130 		.prop = "intel,ixp4xx-eb-hpi-hrdy-pol-high",
135 		.prop = "intel,ixp4xx-eb-mux-address-and-data",
140 		.prop = "intel,ixp4xx-eb-ahb-split-transfers",
145 		.prop = "intel,ixp4xx-eb-write-enable",
150 		.prop = "intel,ixp4xx-eb-byte-access",
168 	if (eb->is_42x && (cs_index > 7)) {  in ixp4xx_exp_setup_chipselect()
169 		dev_err(eb->dev,  in ixp4xx_exp_setup_chipselect()
170 			"invalid chipselect %u, we only support 0-7\n",  in ixp4xx_exp_setup_chipselect()
174 	if (eb->is_43x && (cs_index > 3)) {  in ixp4xx_exp_setup_chipselect()
175 		dev_err(eb->dev,  in ixp4xx_exp_setup_chipselect()
176 			"invalid chipselect %u, we only support 0-3\n",  in ixp4xx_exp_setup_chipselect()
193 	regmap_read(eb->rmap, IXP4XX_EXP_TIMING_CS0 +  in ixp4xx_exp_setup_chipselect()
195 	dev_info(eb->dev, "CS%d at %#08x, size %#08x, config before: %#08x\n",  in ixp4xx_exp_setup_chipselect()
196 		 cs_index, eb->bus_base + IXP4XX_EXP_STRIDE * cs_index,  in ixp4xx_exp_setup_chipselect()
199 	/* Size set-up first align to 2^9 .. 2^24 */  in ixp4xx_exp_setup_chipselect()
205 		dev_err(eb->dev, "illegal size order %d\n", cs_order);  in ixp4xx_exp_setup_chipselect()
208 	dev_dbg(eb->dev, "CS%d size order: %d\n", cs_index, cs_order);  in ixp4xx_exp_setup_chipselect()
210 	cs_cfg |= ((cs_order - 9) << IXP4XX_EXP_SIZE_SHIFT);  in ixp4xx_exp_setup_chipselect()
216 		ret = of_property_read_u32(np, ip->prop, &val);  in ixp4xx_exp_setup_chipselect()
221 		if (ip->max == 1) {  in ixp4xx_exp_setup_chipselect()
223 				cs_cfg |= ip->mask;  in ixp4xx_exp_setup_chipselect()
225 				cs_cfg &= ~ip->mask;  in ixp4xx_exp_setup_chipselect()
226 			dev_info(eb->dev, "CS%d %s %s\n", cs_index,  in ixp4xx_exp_setup_chipselect()
228 				 ip->prop);  in ixp4xx_exp_setup_chipselect()
232 		if (val > ip->max) {  in ixp4xx_exp_setup_chipselect()
233 			dev_err(eb->dev,  in ixp4xx_exp_setup_chipselect()
235 				cs_index, ip->prop, val, ip->max);  in ixp4xx_exp_setup_chipselect()
236 			val = ip->max;  in ixp4xx_exp_setup_chipselect()
239 		cs_cfg &= ~ip->mask;  in ixp4xx_exp_setup_chipselect()
240 		cs_cfg |= (val << ip->shift);  in ixp4xx_exp_setup_chipselect()
241 		dev_info(eb->dev, "CS%d set %s to %u\n", cs_index, ip->prop, val);  in ixp4xx_exp_setup_chipselect()
244 	ret = of_property_read_u32(np, "intel,ixp4xx-eb-cycle-type", &val);  in ixp4xx_exp_setup_chipselect()
247 			dev_err(eb->dev, "illegal cycle type %d\n", val);  in ixp4xx_exp_setup_chipselect()
250 		dev_info(eb->dev, "CS%d set cycle type %d\n", cs_index, val);  in ixp4xx_exp_setup_chipselect()
255 	if (eb->is_42x)  in ixp4xx_exp_setup_chipselect()
257 	if (eb->is_43x) {  in ixp4xx_exp_setup_chipselect()
264 			dev_info(eb->dev, "claims to be Intel strata flash\n");  in ixp4xx_exp_setup_chipselect()
268 	regmap_write(eb->rmap,  in ixp4xx_exp_setup_chipselect()
271 	dev_info(eb->dev, "CS%d wrote %#08x into CS config\n", cs_index, cs_cfg);  in ixp4xx_exp_setup_chipselect()
282 					    cs_size - IXP4XX_EXP_STRIDE);  in ixp4xx_exp_setup_chipselect()
298 	dev_dbg(eb->dev, "child %s has %d register sets\n",  in ixp4xx_exp_setup_child()
321 			dev_err(eb->dev, "illegal CS %d\n", csindex);  in ixp4xx_exp_setup_child()
333 		dev_dbg(eb->dev, "CS%d size %#08x\n", csindex, cssize);  in ixp4xx_exp_setup_child()
349 	struct device *dev = &pdev->dev;  in ixp4xx_exp_probe()
350 	struct device_node *np = dev->of_node;  in ixp4xx_exp_probe()
359 		return -ENOMEM;  in ixp4xx_exp_probe()
361 	eb->dev = dev;  in ixp4xx_exp_probe()
362 	eb->is_42x = of_device_is_compatible(np, "intel,ixp42x-expansion-bus-controller");  in ixp4xx_exp_probe()
363 	eb->is_43x = of_device_is_compatible(np, "intel,ixp43x-expansion-bus-controller");  in ixp4xx_exp_probe()
365 	eb->rmap = syscon_node_to_regmap(np);  in ixp4xx_exp_probe()
366 	if (IS_ERR(eb->rmap))  in ixp4xx_exp_probe()
367 		return dev_err_probe(dev, PTR_ERR(eb->rmap), "no regmap\n");  in ixp4xx_exp_probe()
370 	ret = regmap_read(eb->rmap, IXP4XX_EXP_CNFG0, &val);  in ixp4xx_exp_probe()
374 		eb->bus_base = IXP4XX_EXP_BOOT_BASE;  in ixp4xx_exp_probe()
376 		eb->bus_base = IXP4XX_EXP_NORMAL_BASE;  in ixp4xx_exp_probe()
377 	dev_info(dev, "expansion bus at %08x\n", eb->bus_base);  in ixp4xx_exp_probe()
379 	if (eb->is_43x) {  in ixp4xx_exp_probe()
381 		regmap_read(eb->rmap, IXP43X_EXP_UNIT_FUSE_RESET, &val);  in ixp4xx_exp_probe()
384 			dev_info(dev, "IXP43x at 533 MHz\n");  in ixp4xx_exp_probe()
387 			dev_info(dev, "IXP43x at 400 MHz\n");  in ixp4xx_exp_probe()
390 			dev_info(dev, "IXP43x at 667 MHz\n");  in ixp4xx_exp_probe()
393 			dev_info(dev, "IXP43x unknown speed\n");  in ixp4xx_exp_probe()
412 	{ .compatible = "intel,ixp42x-expansion-bus-controller", },
413 	{ .compatible = "intel,ixp43x-expansion-bus-controller", },
414 	{ .compatible = "intel,ixp45x-expansion-bus-controller", },
415 	{ .compatible = "intel,ixp46x-expansion-bus-controller", },
422 		.name = "intel-extbus",
428 MODULE_DESCRIPTION("Intel IXP4xx external bus driver");