Lines Matching +full:on +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0
25 const struct regmap_irq_chip *chip; member
52 const struct regmap_irq_chip *chip = data->chip; in sub_irq_reg() local
53 struct regmap *map = data->map; in sub_irq_reg()
58 if (!chip->sub_reg_offsets || !chip->not_fixed_stride) { in sub_irq_reg()
60 reg = base_reg + (i * map->reg_stride * data->irq_reg_stride); in sub_irq_reg()
62 subreg = &chip->sub_reg_offsets[i]; in sub_irq_reg()
63 offset = subreg->offset[0]; in sub_irq_reg()
74 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
81 mutex_lock(&d->lock); in regmap_irq_lock()
88 if (d->chip->mask_writeonly) in regmap_irq_update_bits()
89 return regmap_write_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
91 return regmap_update_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
97 struct regmap *map = d->map; in regmap_irq_sync_unlock()
103 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
104 ret = pm_runtime_get_sync(map->dev); in regmap_irq_sync_unlock()
106 dev_err(map->dev, "IRQ sync failed to resume: %d\n", in regmap_irq_sync_unlock()
110 if (d->clear_status) { in regmap_irq_sync_unlock()
111 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
112 reg = sub_irq_reg(d, d->chip->status_base, i); in regmap_irq_sync_unlock()
116 dev_err(d->map->dev, in regmap_irq_sync_unlock()
120 d->clear_status = false; in regmap_irq_sync_unlock()
125 * hardware. We rely on the use of the regmap core cache to in regmap_irq_sync_unlock()
128 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
129 if (!d->chip->mask_base) in regmap_irq_sync_unlock()
132 reg = sub_irq_reg(d, d->chip->mask_base, i); in regmap_irq_sync_unlock()
133 if (d->chip->mask_invert) { in regmap_irq_sync_unlock()
135 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
136 } else if (d->chip->unmask_base) { in regmap_irq_sync_unlock()
139 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
141 dev_err(d->map->dev, in regmap_irq_sync_unlock()
144 unmask_offset = d->chip->unmask_base - in regmap_irq_sync_unlock()
145 d->chip->mask_base; in regmap_irq_sync_unlock()
149 d->mask_buf_def[i], in regmap_irq_sync_unlock()
150 d->mask_buf[i]); in regmap_irq_sync_unlock()
153 d->mask_buf_def[i], d->mask_buf[i]); in regmap_irq_sync_unlock()
156 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
159 reg = sub_irq_reg(d, d->chip->wake_base, i); in regmap_irq_sync_unlock()
160 if (d->wake_buf) { in regmap_irq_sync_unlock()
161 if (d->chip->wake_invert) in regmap_irq_sync_unlock()
163 d->mask_buf_def[i], in regmap_irq_sync_unlock()
164 ~d->wake_buf[i]); in regmap_irq_sync_unlock()
167 d->mask_buf_def[i], in regmap_irq_sync_unlock()
168 d->wake_buf[i]); in regmap_irq_sync_unlock()
170 dev_err(d->map->dev, in regmap_irq_sync_unlock()
175 if (!d->chip->init_ack_masked) in regmap_irq_sync_unlock()
182 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { in regmap_irq_sync_unlock()
183 reg = sub_irq_reg(d, d->chip->ack_base, i); in regmap_irq_sync_unlock()
186 if (d->chip->ack_invert) in regmap_irq_sync_unlock()
187 ret = regmap_write(map, reg, ~d->mask_buf[i]); in regmap_irq_sync_unlock()
189 ret = regmap_write(map, reg, d->mask_buf[i]); in regmap_irq_sync_unlock()
190 if (d->chip->clear_ack) { in regmap_irq_sync_unlock()
191 if (d->chip->ack_invert && !ret) in regmap_irq_sync_unlock()
193 d->mask_buf[i]); in regmap_irq_sync_unlock()
196 ~d->mask_buf[i]); in regmap_irq_sync_unlock()
199 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_sync_unlock()
205 if (!d->chip->type_in_mask) { in regmap_irq_sync_unlock()
206 for (i = 0; i < d->chip->num_type_reg; i++) { in regmap_irq_sync_unlock()
207 if (!d->type_buf_def[i]) in regmap_irq_sync_unlock()
209 reg = sub_irq_reg(d, d->chip->type_base, i); in regmap_irq_sync_unlock()
210 if (d->chip->type_invert) in regmap_irq_sync_unlock()
212 d->type_buf_def[i], ~d->type_buf[i]); in regmap_irq_sync_unlock()
215 d->type_buf_def[i], d->type_buf[i]); in regmap_irq_sync_unlock()
217 dev_err(d->map->dev, "Failed to sync type in %x\n", in regmap_irq_sync_unlock()
222 if (d->chip->num_virt_regs) { in regmap_irq_sync_unlock()
223 for (i = 0; i < d->chip->num_virt_regs; i++) { in regmap_irq_sync_unlock()
224 for (j = 0; j < d->chip->num_regs; j++) { in regmap_irq_sync_unlock()
225 reg = sub_irq_reg(d, d->chip->virt_reg_base[i], in regmap_irq_sync_unlock()
227 ret = regmap_write(map, reg, d->virt_buf[i][j]); in regmap_irq_sync_unlock()
229 dev_err(d->map->dev, in regmap_irq_sync_unlock()
236 if (d->chip->runtime_pm) in regmap_irq_sync_unlock()
237 pm_runtime_put(map->dev); in regmap_irq_sync_unlock()
240 if (d->wake_count < 0) in regmap_irq_sync_unlock()
241 for (i = d->wake_count; i < 0; i++) in regmap_irq_sync_unlock()
242 irq_set_irq_wake(d->irq, 0); in regmap_irq_sync_unlock()
243 else if (d->wake_count > 0) in regmap_irq_sync_unlock()
244 for (i = 0; i < d->wake_count; i++) in regmap_irq_sync_unlock()
245 irq_set_irq_wake(d->irq, 1); in regmap_irq_sync_unlock()
247 d->wake_count = 0; in regmap_irq_sync_unlock()
249 mutex_unlock(&d->lock); in regmap_irq_sync_unlock()
255 struct regmap *map = d->map; in regmap_irq_enable()
256 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_enable()
259 type = irq_data->type.type_falling_val | irq_data->type.type_rising_val; in regmap_irq_enable()
272 if (d->chip->type_in_mask && type) in regmap_irq_enable()
273 mask = d->type_buf[irq_data->reg_offset / map->reg_stride]; in regmap_irq_enable()
275 mask = irq_data->mask; in regmap_irq_enable()
277 if (d->chip->clear_on_unmask) in regmap_irq_enable()
278 d->clear_status = true; in regmap_irq_enable()
280 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask; in regmap_irq_enable()
286 struct regmap *map = d->map; in regmap_irq_disable()
287 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_disable()
289 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
295 struct regmap *map = d->map; in regmap_irq_set_type()
296 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_type()
298 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type()
300 if ((t->types_supported & type) != type) in regmap_irq_set_type()
303 reg = t->type_reg_offset / map->reg_stride; in regmap_irq_set_type()
305 if (t->type_reg_mask) in regmap_irq_set_type()
306 d->type_buf[reg] &= ~t->type_reg_mask; in regmap_irq_set_type()
308 d->type_buf[reg] &= ~(t->type_falling_val | in regmap_irq_set_type()
309 t->type_rising_val | in regmap_irq_set_type()
310 t->type_level_low_val | in regmap_irq_set_type()
311 t->type_level_high_val); in regmap_irq_set_type()
314 d->type_buf[reg] |= t->type_falling_val; in regmap_irq_set_type()
318 d->type_buf[reg] |= t->type_rising_val; in regmap_irq_set_type()
322 d->type_buf[reg] |= (t->type_falling_val | in regmap_irq_set_type()
323 t->type_rising_val); in regmap_irq_set_type()
327 d->type_buf[reg] |= t->type_level_high_val; in regmap_irq_set_type()
331 d->type_buf[reg] |= t->type_level_low_val; in regmap_irq_set_type()
334 return -EINVAL; in regmap_irq_set_type()
337 if (d->chip->set_type_virt) in regmap_irq_set_type()
338 return d->chip->set_type_virt(d->virt_buf, type, data->hwirq, in regmap_irq_set_type()
344 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on) in regmap_irq_set_wake() argument
347 struct regmap *map = d->map; in regmap_irq_set_wake()
348 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_wake()
350 if (on) { in regmap_irq_set_wake()
351 if (d->wake_buf) in regmap_irq_set_wake()
352 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
353 &= ~irq_data->mask; in regmap_irq_set_wake()
354 d->wake_count++; in regmap_irq_set_wake()
356 if (d->wake_buf) in regmap_irq_set_wake()
357 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
358 |= irq_data->mask; in regmap_irq_set_wake()
359 d->wake_count--; in regmap_irq_set_wake()
377 const struct regmap_irq_chip *chip = data->chip; in read_sub_irq_data() local
378 struct regmap *map = data->map; in read_sub_irq_data()
382 if (!chip->sub_reg_offsets) { in read_sub_irq_data()
384 ret = regmap_read(map, chip->status_base + in read_sub_irq_data()
385 (b * map->reg_stride * data->irq_reg_stride), in read_sub_irq_data()
386 &data->status_buf[b]); in read_sub_irq_data()
388 subreg = &chip->sub_reg_offsets[b]; in read_sub_irq_data()
389 for (i = 0; i < subreg->num_regs; i++) { in read_sub_irq_data()
390 unsigned int offset = subreg->offset[i]; in read_sub_irq_data()
392 if (chip->not_fixed_stride) in read_sub_irq_data()
394 chip->status_base + offset, in read_sub_irq_data()
395 &data->status_buf[b]); in read_sub_irq_data()
398 chip->status_base + offset, in read_sub_irq_data()
399 &data->status_buf[offset]); in read_sub_irq_data()
411 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_thread() local
412 struct regmap *map = data->map; in regmap_irq_thread()
417 if (chip->handle_pre_irq) in regmap_irq_thread()
418 chip->handle_pre_irq(chip->irq_drv_data); in regmap_irq_thread()
420 if (chip->runtime_pm) { in regmap_irq_thread()
421 ret = pm_runtime_get_sync(map->dev); in regmap_irq_thread()
423 dev_err(map->dev, "IRQ thread failed to resume: %d\n", in regmap_irq_thread()
430 * Read only registers with active IRQs if the chip has 'main status in regmap_irq_thread()
435 if (chip->num_main_regs) { in regmap_irq_thread()
439 size = chip->num_regs * sizeof(unsigned int); in regmap_irq_thread()
441 max_main_bits = (chip->num_main_status_bits) ? in regmap_irq_thread()
442 chip->num_main_status_bits : chip->num_regs; in regmap_irq_thread()
444 memset(data->status_buf, 0, size); in regmap_irq_thread()
451 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
452 ret = regmap_read(map, chip->main_status + in regmap_irq_thread()
453 (i * map->reg_stride in regmap_irq_thread()
454 * data->irq_reg_stride), in regmap_irq_thread()
455 &data->main_status_buf[i]); in regmap_irq_thread()
457 dev_err(map->dev, in regmap_irq_thread()
465 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
467 const unsigned long mreg = data->main_status_buf[i]; in regmap_irq_thread()
469 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { in regmap_irq_thread()
470 if (i * map->format.val_bytes * 8 + b > in regmap_irq_thread()
476 dev_err(map->dev, in regmap_irq_thread()
484 } else if (!map->use_single_read && map->reg_stride == 1 && in regmap_irq_thread()
485 data->irq_reg_stride == 1) { in regmap_irq_thread()
487 u8 *buf8 = data->status_reg_buf; in regmap_irq_thread()
488 u16 *buf16 = data->status_reg_buf; in regmap_irq_thread()
489 u32 *buf32 = data->status_reg_buf; in regmap_irq_thread()
491 BUG_ON(!data->status_reg_buf); in regmap_irq_thread()
493 ret = regmap_bulk_read(map, chip->status_base, in regmap_irq_thread()
494 data->status_reg_buf, in regmap_irq_thread()
495 chip->num_regs); in regmap_irq_thread()
497 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_irq_thread()
502 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
503 switch (map->format.val_bytes) { in regmap_irq_thread()
505 data->status_buf[i] = buf8[i]; in regmap_irq_thread()
508 data->status_buf[i] = buf16[i]; in regmap_irq_thread()
511 data->status_buf[i] = buf32[i]; in regmap_irq_thread()
520 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
522 data->chip->status_base, i); in regmap_irq_thread()
523 ret = regmap_read(map, reg, &data->status_buf[i]); in regmap_irq_thread()
526 dev_err(map->dev, in regmap_irq_thread()
534 if (chip->status_invert) in regmap_irq_thread()
535 for (i = 0; i < data->chip->num_regs; i++) in regmap_irq_thread()
536 data->status_buf[i] = ~data->status_buf[i]; in regmap_irq_thread()
545 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
546 data->status_buf[i] &= ~data->mask_buf[i]; in regmap_irq_thread()
548 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_irq_thread()
549 reg = sub_irq_reg(data, data->chip->ack_base, i); in regmap_irq_thread()
551 if (chip->ack_invert) in regmap_irq_thread()
553 ~data->status_buf[i]); in regmap_irq_thread()
556 data->status_buf[i]); in regmap_irq_thread()
557 if (chip->clear_ack) { in regmap_irq_thread()
558 if (chip->ack_invert && !ret) in regmap_irq_thread()
560 data->status_buf[i]); in regmap_irq_thread()
563 ~data->status_buf[i]); in regmap_irq_thread()
566 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_thread()
571 for (i = 0; i < chip->num_irqs; i++) { in regmap_irq_thread()
572 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
573 map->reg_stride] & chip->irqs[i].mask) { in regmap_irq_thread()
574 handle_nested_irq(irq_find_mapping(data->domain, i)); in regmap_irq_thread()
580 if (chip->runtime_pm) in regmap_irq_thread()
581 pm_runtime_put(map->dev); in regmap_irq_thread()
583 if (chip->handle_post_irq) in regmap_irq_thread()
584 chip->handle_post_irq(chip->irq_drv_data); in regmap_irq_thread()
595 struct regmap_irq_chip_data *data = h->host_data; in regmap_irq_map()
598 irq_set_chip(virq, &data->irq_chip); in regmap_irq_map()
600 irq_set_parent(virq, data->irq); in regmap_irq_map()
612 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
619 * @chip: Configuration for the interrupt controller.
620 * @data: Runtime data structure for the controller, allocated on success.
622 * Returns 0 on success or an errno on failure.
624 * In order for this to be efficient the chip really should use a
625 * register cache. The chip driver is responsible for restoring the
631 const struct regmap_irq_chip *chip, in regmap_add_irq_chip_fwnode() argument
636 int ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
641 if (chip->num_regs <= 0) in regmap_add_irq_chip_fwnode()
642 return -EINVAL; in regmap_add_irq_chip_fwnode()
644 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) in regmap_add_irq_chip_fwnode()
645 return -EINVAL; in regmap_add_irq_chip_fwnode()
647 for (i = 0; i < chip->num_irqs; i++) { in regmap_add_irq_chip_fwnode()
648 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip_fwnode()
649 return -EINVAL; in regmap_add_irq_chip_fwnode()
650 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip_fwnode()
651 chip->num_regs) in regmap_add_irq_chip_fwnode()
652 return -EINVAL; in regmap_add_irq_chip_fwnode()
655 if (chip->not_fixed_stride) { in regmap_add_irq_chip_fwnode()
656 for (i = 0; i < chip->num_regs; i++) in regmap_add_irq_chip_fwnode()
657 if (chip->sub_reg_offsets[i].num_regs != 1) in regmap_add_irq_chip_fwnode()
658 return -EINVAL; in regmap_add_irq_chip_fwnode()
662 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); in regmap_add_irq_chip_fwnode()
664 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", in regmap_add_irq_chip_fwnode()
672 return -ENOMEM; in regmap_add_irq_chip_fwnode()
674 if (chip->num_main_regs) { in regmap_add_irq_chip_fwnode()
675 d->main_status_buf = kcalloc(chip->num_main_regs, in regmap_add_irq_chip_fwnode()
679 if (!d->main_status_buf) in regmap_add_irq_chip_fwnode()
683 d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
685 if (!d->status_buf) in regmap_add_irq_chip_fwnode()
688 d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
690 if (!d->mask_buf) in regmap_add_irq_chip_fwnode()
693 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
695 if (!d->mask_buf_def) in regmap_add_irq_chip_fwnode()
698 if (chip->wake_base) { in regmap_add_irq_chip_fwnode()
699 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
701 if (!d->wake_buf) in regmap_add_irq_chip_fwnode()
705 num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg; in regmap_add_irq_chip_fwnode()
707 d->type_buf_def = kcalloc(num_type_reg, in regmap_add_irq_chip_fwnode()
709 if (!d->type_buf_def) in regmap_add_irq_chip_fwnode()
712 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
714 if (!d->type_buf) in regmap_add_irq_chip_fwnode()
718 if (chip->num_virt_regs) { in regmap_add_irq_chip_fwnode()
720 * Create virt_buf[chip->num_extra_config_regs][chip->num_regs] in regmap_add_irq_chip_fwnode()
722 d->virt_buf = kcalloc(chip->num_virt_regs, sizeof(*d->virt_buf), in regmap_add_irq_chip_fwnode()
724 if (!d->virt_buf) in regmap_add_irq_chip_fwnode()
727 for (i = 0; i < chip->num_virt_regs; i++) { in regmap_add_irq_chip_fwnode()
728 d->virt_buf[i] = kcalloc(chip->num_regs, in regmap_add_irq_chip_fwnode()
731 if (!d->virt_buf[i]) in regmap_add_irq_chip_fwnode()
736 d->irq_chip = regmap_irq_chip; in regmap_add_irq_chip_fwnode()
737 d->irq_chip.name = chip->name; in regmap_add_irq_chip_fwnode()
738 d->irq = irq; in regmap_add_irq_chip_fwnode()
739 d->map = map; in regmap_add_irq_chip_fwnode()
740 d->chip = chip; in regmap_add_irq_chip_fwnode()
741 d->irq_base = irq_base; in regmap_add_irq_chip_fwnode()
743 if (chip->irq_reg_stride) in regmap_add_irq_chip_fwnode()
744 d->irq_reg_stride = chip->irq_reg_stride; in regmap_add_irq_chip_fwnode()
746 d->irq_reg_stride = 1; in regmap_add_irq_chip_fwnode()
748 if (chip->type_reg_stride) in regmap_add_irq_chip_fwnode()
749 d->type_reg_stride = chip->type_reg_stride; in regmap_add_irq_chip_fwnode()
751 d->type_reg_stride = 1; in regmap_add_irq_chip_fwnode()
753 if (!map->use_single_read && map->reg_stride == 1 && in regmap_add_irq_chip_fwnode()
754 d->irq_reg_stride == 1) { in regmap_add_irq_chip_fwnode()
755 d->status_reg_buf = kmalloc_array(chip->num_regs, in regmap_add_irq_chip_fwnode()
756 map->format.val_bytes, in regmap_add_irq_chip_fwnode()
758 if (!d->status_reg_buf) in regmap_add_irq_chip_fwnode()
762 mutex_init(&d->lock); in regmap_add_irq_chip_fwnode()
764 for (i = 0; i < chip->num_irqs; i++) in regmap_add_irq_chip_fwnode()
765 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip_fwnode()
766 |= chip->irqs[i].mask; in regmap_add_irq_chip_fwnode()
769 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
770 d->mask_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
771 if (!chip->mask_base) in regmap_add_irq_chip_fwnode()
774 reg = sub_irq_reg(d, d->chip->mask_base, i); in regmap_add_irq_chip_fwnode()
776 if (chip->mask_invert) in regmap_add_irq_chip_fwnode()
778 d->mask_buf[i], ~d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
779 else if (d->chip->unmask_base) { in regmap_add_irq_chip_fwnode()
780 unmask_offset = d->chip->unmask_base - in regmap_add_irq_chip_fwnode()
781 d->chip->mask_base; in regmap_add_irq_chip_fwnode()
784 d->mask_buf[i], in regmap_add_irq_chip_fwnode()
785 d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
788 d->mask_buf[i], d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
790 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
795 if (!chip->init_ack_masked) in regmap_add_irq_chip_fwnode()
799 reg = sub_irq_reg(d, d->chip->status_base, i); in regmap_add_irq_chip_fwnode()
800 ret = regmap_read(map, reg, &d->status_buf[i]); in regmap_add_irq_chip_fwnode()
802 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_add_irq_chip_fwnode()
807 if (chip->status_invert) in regmap_add_irq_chip_fwnode()
808 d->status_buf[i] = ~d->status_buf[i]; in regmap_add_irq_chip_fwnode()
810 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_add_irq_chip_fwnode()
811 reg = sub_irq_reg(d, d->chip->ack_base, i); in regmap_add_irq_chip_fwnode()
812 if (chip->ack_invert) in regmap_add_irq_chip_fwnode()
814 ~(d->status_buf[i] & d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
817 d->status_buf[i] & d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
818 if (chip->clear_ack) { in regmap_add_irq_chip_fwnode()
819 if (chip->ack_invert && !ret) in regmap_add_irq_chip_fwnode()
821 (d->status_buf[i] & in regmap_add_irq_chip_fwnode()
822 d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
825 ~(d->status_buf[i] & in regmap_add_irq_chip_fwnode()
826 d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
829 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
837 if (d->wake_buf) { in regmap_add_irq_chip_fwnode()
838 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
839 d->wake_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
840 reg = sub_irq_reg(d, d->chip->wake_base, i); in regmap_add_irq_chip_fwnode()
842 if (chip->wake_invert) in regmap_add_irq_chip_fwnode()
844 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
848 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
849 d->wake_buf[i]); in regmap_add_irq_chip_fwnode()
851 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
858 if (chip->num_type_reg && !chip->type_in_mask) { in regmap_add_irq_chip_fwnode()
859 for (i = 0; i < chip->num_type_reg; ++i) { in regmap_add_irq_chip_fwnode()
860 reg = sub_irq_reg(d, d->chip->type_base, i); in regmap_add_irq_chip_fwnode()
862 ret = regmap_read(map, reg, &d->type_buf_def[i]); in regmap_add_irq_chip_fwnode()
864 if (d->chip->type_invert) in regmap_add_irq_chip_fwnode()
865 d->type_buf_def[i] = ~d->type_buf_def[i]; in regmap_add_irq_chip_fwnode()
868 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
876 d->domain = irq_domain_create_legacy(fwnode, chip->num_irqs, in regmap_add_irq_chip_fwnode()
880 d->domain = irq_domain_create_linear(fwnode, chip->num_irqs, in regmap_add_irq_chip_fwnode()
882 if (!d->domain) { in regmap_add_irq_chip_fwnode()
883 dev_err(map->dev, "Failed to create IRQ domain\n"); in regmap_add_irq_chip_fwnode()
884 ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
890 chip->name, d); in regmap_add_irq_chip_fwnode()
892 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", in regmap_add_irq_chip_fwnode()
893 irq, chip->name, ret); in regmap_add_irq_chip_fwnode()
904 kfree(d->type_buf); in regmap_add_irq_chip_fwnode()
905 kfree(d->type_buf_def); in regmap_add_irq_chip_fwnode()
906 kfree(d->wake_buf); in regmap_add_irq_chip_fwnode()
907 kfree(d->mask_buf_def); in regmap_add_irq_chip_fwnode()
908 kfree(d->mask_buf); in regmap_add_irq_chip_fwnode()
909 kfree(d->status_buf); in regmap_add_irq_chip_fwnode()
910 kfree(d->status_reg_buf); in regmap_add_irq_chip_fwnode()
911 if (d->virt_buf) { in regmap_add_irq_chip_fwnode()
912 for (i = 0; i < chip->num_virt_regs; i++) in regmap_add_irq_chip_fwnode()
913 kfree(d->virt_buf[i]); in regmap_add_irq_chip_fwnode()
914 kfree(d->virt_buf); in regmap_add_irq_chip_fwnode()
922 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
928 * @chip: Configuration for the interrupt controller.
929 * @data: Runtime data structure for the controller, allocated on success.
931 * Returns 0 on success or an errno on failure.
937 int irq_base, const struct regmap_irq_chip *chip, in regmap_add_irq_chip() argument
940 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, in regmap_add_irq_chip()
941 irq_flags, irq_base, chip, data); in regmap_add_irq_chip()
946 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
951 * This function also disposes of all mapped IRQs on the chip.
964 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { in regmap_del_irq_chip()
966 if (!d->chip->irqs[hwirq].mask) in regmap_del_irq_chip()
970 * Find the virtual irq of hwirq on chip and if it is in regmap_del_irq_chip()
973 virq = irq_find_mapping(d->domain, hwirq); in regmap_del_irq_chip()
978 irq_domain_remove(d->domain); in regmap_del_irq_chip()
979 kfree(d->type_buf); in regmap_del_irq_chip()
980 kfree(d->type_buf_def); in regmap_del_irq_chip()
981 kfree(d->wake_buf); in regmap_del_irq_chip()
982 kfree(d->mask_buf_def); in regmap_del_irq_chip()
983 kfree(d->mask_buf); in regmap_del_irq_chip()
984 kfree(d->status_reg_buf); in regmap_del_irq_chip()
985 kfree(d->status_buf); in regmap_del_irq_chip()
994 regmap_del_irq_chip(d->irq, d); in devm_regmap_irq_chip_release()
1010 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1012 * @dev: The device pointer on which irq_chip belongs to.
1018 * @chip: Configuration for the interrupt controller.
1019 * @data: Runtime data structure for the controller, allocated on success
1021 * Returns 0 on success or an errno on failure.
1030 const struct regmap_irq_chip *chip, in devm_regmap_add_irq_chip_fwnode() argument
1039 return -ENOMEM; in devm_regmap_add_irq_chip_fwnode()
1042 chip, &d); in devm_regmap_add_irq_chip_fwnode()
1056 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
1058 * @dev: The device pointer on which irq_chip belongs to.
1063 * @chip: Configuration for the interrupt controller.
1064 * @data: Runtime data structure for the controller, allocated on success
1066 * Returns 0 on success or an errno on failure.
1073 const struct regmap_irq_chip *chip, in devm_regmap_add_irq_chip() argument
1076 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, in devm_regmap_add_irq_chip()
1077 irq, irq_flags, irq_base, chip, in devm_regmap_add_irq_chip()
1083 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1096 WARN_ON(irq != data->irq); in devm_regmap_del_irq_chip()
1106 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1108 * @data: regmap irq controller to operate on.
1114 WARN_ON(!data->irq_base); in regmap_irq_chip_get_base()
1115 return data->irq_base; in regmap_irq_chip_get_base()
1120 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1122 * @data: regmap irq controller to operate on.
1123 * @irq: index of the interrupt requested in the chip IRQs.
1130 if (!data->chip->irqs[irq].mask) in regmap_irq_get_virq()
1131 return -EINVAL; in regmap_irq_get_virq()
1133 return irq_create_mapping(data->domain, irq); in regmap_irq_get_virq()
1138 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1140 * @data: regmap_irq controller to operate on.
1150 return data->domain; in regmap_irq_get_domain()