Lines Matching +full:0 +full:xaa00
70 #define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8))
85 |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0;
87 module_param(IA_TX_BUF, int, 0);
88 module_param(IA_TX_BUF_SZ, int, 0);
89 module_param(IA_RX_BUF, int, 0);
90 module_param(IA_RX_BUF_SZ, int, 0);
148 tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff; in ia_hack_tcq()
154 *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0; in ia_hack_tcq()
162 dev->desc_tbl[desc1 -1].timestamp = 0; in ia_hack_tcq()
163 IF_EVENT(printk("ia_hack: return_q skb = 0x%p desc = %d\n", in ia_hack_tcq()
167 if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0) in ia_hack_tcq()
184 static unsigned long timer = 0; in get_desc()
190 i=0; in get_desc()
210 dev->desc_tbl[i].timestamp = 0; in get_desc()
218 return 0xFFFF; in get_desc()
228 return 0xFFFF; in get_desc()
249 foundLockUp = 0; in clear_lockup()
250 if( vcstatus->cnt == 0x05 ) { in clear_lockup()
254 if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) { in clear_lockup()
257 if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE)) in clear_lockup()
270 vcstatus->cnt = 0; in clear_lockup()
275 writew(0xFFFD, dev->seg_reg+MODE_REG_0); in clear_lockup()
278 abr_vc->status &= 0xFFF8; in clear_lockup()
279 abr_vc->status |= 0x0001; /* state is idle */ in clear_lockup()
281 for( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ ); in clear_lockup()
289 vcstatus->cnt = 0; in clear_lockup()
304 ** R = reserved (written as 0)
305 ** NZ = 0 if 0 cells/sec; 1 otherwise
313 #define NZ 0x4000 in cellrate_to_float()
316 #define M_MASK 0x1ff in cellrate_to_float()
317 #define E_MASK 0x1f in cellrate_to_float()
319 u32 tmp = cr & 0x00ffffff; in cellrate_to_float()
320 int i = 0; in cellrate_to_float()
321 if (cr == 0) in cellrate_to_float()
322 return 0; in cellrate_to_float()
336 #if 0
344 if ((rate & NZ) == 0)
345 return 0;
348 if (exp == 0)
364 srv_p->mcr = 0; in init_abr_vc()
365 srv_p->icr = 0x055cb7; in init_abr_vc()
366 srv_p->tbe = 0xffffff; in init_abr_vc()
367 srv_p->frtt = 0x3a; in init_abr_vc()
368 srv_p->rif = 0xf; in init_abr_vc()
369 srv_p->rdf = 0xb; in init_abr_vc()
370 srv_p->nrm = 0x4; in init_abr_vc()
371 srv_p->trm = 0x7; in init_abr_vc()
372 srv_p->cdf = 0x3; in init_abr_vc()
389 #if 0 /* sanity check */ in ia_open_abr_vc()
390 if (srv_p->pcr == 0) in ia_open_abr_vc()
412 else if (srv_p->adtf == 0) in ia_open_abr_vc()
421 memset ((caddr_t)f_abr_vc, 0, sizeof(*f_abr_vc)); in ia_open_abr_vc()
427 if ( trm == 0) trm = 1; in ia_open_abr_vc()
428 f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm; in ia_open_abr_vc()
430 if (crm == 0) crm = 1; in ia_open_abr_vc()
431 f_abr_vc->f_crm = crm & 0xff; in ia_open_abr_vc()
438 if (adtf == 0) adtf = 1; in ia_open_abr_vc()
439 f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff; in ia_open_abr_vc()
442 f_abr_vc->f_status = 0x0042; in ia_open_abr_vc()
444 case 0: /* RFRED initialization */ in ia_open_abr_vc()
449 r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f; in ia_open_abr_vc()
451 if (air == 0) air = 1; in ia_open_abr_vc()
460 return 0; in ia_open_abr_vc()
463 u32 rateLow=0, rateHigh, rate; in ia_cbr_setup()
467 int idealSlot =0, testSlot, toBeAssigned, inc; in ia_cbr_setup()
471 u32 fracSlot = 0; in ia_cbr_setup()
472 u32 sp_mod = 0; in ia_cbr_setup()
473 u32 sp_mod2 = 0; in ia_cbr_setup()
476 if (vcc->qos.txtp.max_pcr <= 0) { in ia_cbr_setup()
482 IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n", in ia_cbr_setup()
492 IF_CBR(printk("Entries = 0x%x, CbrRemEntries = 0x%x.\n", in ia_cbr_setup()
503 cbrVC = 0; in ia_cbr_setup()
507 fracSlot = 0; in ia_cbr_setup()
509 IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);) in ia_cbr_setup()
531 inc = 0; in ia_cbr_setup()
534 IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%p, NumToAssign=%d\n", in ia_cbr_setup()
541 if (testSlot < 0) { // Wrap if necessary in ia_cbr_setup()
543 IF_CBR(printk("Testslot Wrap. STable Start=0x%p,Testslot=%d\n", in ia_cbr_setup()
554 IF_CBR(printk(" Testslot=0x%x ToBeAssgned=%d\n", in ia_cbr_setup()
559 IF_CBR(printk("Reading CBR Tbl from 0x%p, CbrVal=0x%x Iteration %d\n", in ia_cbr_setup()
572 writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS); in ia_cbr_setup()
575 return 0; in ia_cbr_setup()
579 u16 *SchedTbl, NullVci = 0; in ia_cbrVc_close()
585 if (iadev->NumEnabledCBR == 0) { in ia_cbrVc_close()
586 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); in ia_cbrVc_close()
589 NumFound = 0; in ia_cbrVc_close()
590 for (i=0; i < iadev->CbrTotEntries; i++) in ia_cbrVc_close()
603 int tmp = 0; in ia_avail_descs()
637 return 0; in ia_que_tx()
673 if ((vcc->pop) && (skb1->len != 0)) in ia_tx_poll()
676 IF_EVENT(printk("Transmit Done - skb 0x%lx return\n", in ia_tx_poll()
688 if ((vcc->pop) && (skb->len != 0)) in ia_tx_poll()
691 IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);) in ia_tx_poll()
701 #if 0
718 for (i=15; i>=0; i--) {
719 NVRAM_CLKOUT (val & 0x8000);
752 val = 0; in ia_eeprom_get()
753 for (i=15; i>=0; i--) { in ia_eeprom_get()
799 #if 0
809 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
839 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
843 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
847 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
850 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
859 #if 0
863 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
866 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
886 { SUNI_DS3_FRM_INTR_ENBL, 0x17 },
887 { SUNI_DS3_FRM_CFG, 0x01 },
888 { SUNI_DS3_TRAN_CFG, 0x01 },
889 { SUNI_CONFIG, 0 },
890 { SUNI_SPLR_CFG, 0 },
891 { SUNI_SPLT_CFG, 0 }
896 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
904 { SUNI_E3_FRM_FRAM_OPTIONS, 0x04 },
905 { SUNI_E3_FRM_MAINT_OPTIONS, 0x20 },
906 { SUNI_E3_FRM_FRAM_INTR_ENBL, 0x1d },
907 { SUNI_E3_FRM_MAINT_INTR_ENBL, 0x30 },
908 { SUNI_E3_TRAN_STAT_DIAG_OPTIONS, 0 },
909 { SUNI_E3_TRAN_FRAM_OPTIONS, 0x01 },
911 { SUNI_SPLR_CFG, 0x41 },
912 { SUNI_SPLT_CFG, 0x41 }
917 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
925 { SUNI_INTR_ENBL, 0x28 },
927 { SUNI_ID_RESET, 0 },
929 { SUNI_MASTER_TEST, 0 },
931 { SUNI_RXCP_CTRL, 0x2c },
932 { SUNI_RXCP_FCTRL, 0x81 },
934 { SUNI_RXCP_IDLE_PAT_H1, 0 },
935 { SUNI_RXCP_IDLE_PAT_H2, 0 },
936 { SUNI_RXCP_IDLE_PAT_H3, 0 },
937 { SUNI_RXCP_IDLE_PAT_H4, 0x01 },
939 { SUNI_RXCP_IDLE_MASK_H1, 0xff },
940 { SUNI_RXCP_IDLE_MASK_H2, 0xff },
941 { SUNI_RXCP_IDLE_MASK_H3, 0xff },
942 { SUNI_RXCP_IDLE_MASK_H4, 0xfe },
944 { SUNI_RXCP_CELL_PAT_H1, 0 },
945 { SUNI_RXCP_CELL_PAT_H2, 0 },
946 { SUNI_RXCP_CELL_PAT_H3, 0 },
947 { SUNI_RXCP_CELL_PAT_H4, 0x01 },
949 { SUNI_RXCP_CELL_MASK_H1, 0xff },
950 { SUNI_RXCP_CELL_MASK_H2, 0xff },
951 { SUNI_RXCP_CELL_MASK_H3, 0xff },
952 { SUNI_RXCP_CELL_MASK_H4, 0xff },
954 { SUNI_TXCP_CTRL, 0xa4 },
955 { SUNI_TXCP_INTR_EN_STS, 0x10 },
956 { SUNI_TXCP_IDLE_PAT_H5, 0x55 }
979 static int tcnter = 0;
985 count = 0;
988 for(col = 0;count + col < length && col < 16; col++){
989 if (col != 0 && (col % 4) == 0)
994 if ((col % 4) == 0)
999 for(col = 0;count + col < length && col < 16; col++){
1035 printk("B_tcq_wr = 0x%x desc = %d last desc = %d\n",
1038 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1042 printk("tcq_st_ptr = 0x%x tcq_ed_ptr = 0x%x \n", tcq_st_ptr, tcq_ed_ptr);
1043 i = 0;
1049 for(i=0; i <iadev->num_tx_desc; i++)
1058 #if 0 /* closing the receiving size will cause too many excp int */
1065 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1068 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1074 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1077 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1078 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1080 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1110 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1116 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1117 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1119 printk(" pcq_wr_ptr = 0x%x\n",
1120 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1135 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1140 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1206 out: return 0;
1219 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1220 IF_EVENT(printk("rx_intr: status = 0x%x\n", status);)
1229 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1234 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1243 iadev->rxing = 0;
1246 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1305 printk("rx_dle_intr: skb len 0\n");
1366 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1368 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1384 if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
1406 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1418 return 0;
1425 unsigned long rx_pkt_start = 0;
1453 writel(iadev->rx_dle_dma & 0xfffff000,
1455 IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n",
1458 printk("Rx Dle list addr: 0x%p value: 0x%0x\n",
1462 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1463 writew(0, iadev->reass_reg+MODE_REG);
1469 Buffer descr 0x0000 (736 - 23K)
1470 VP Table 0x5c00 (256 - 512)
1471 Except q 0x5e00 (128 - 512)
1472 Free buffer q 0x6000 (1K - 2K)
1473 Packet comp q 0x6800 (1K - 2K)
1474 Reass Table 0x7000 (1K - 2K)
1475 VC Table 0x7800 (1K - 2K)
1476 ABR VC Table 0x8000 (1K - 32K)
1487 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1492 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1494 buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
1498 IF_INIT(printk("Rx Buffer desc ptr: 0x%p\n", buf_desc_ptr);)
1515 IF_INIT(printk("freeq_start: 0x%p\n", freeq_start);)
1517 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1524 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1532 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1533 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1534 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1535 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1536 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1537 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1538 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1539 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1541 IF_INIT(printk("INIT:pcq_st:0x%x pcq_ed:0x%x pcq_rd:0x%x pcq_wr:0x%x",
1546 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1548 - I guess we can write all 1s or 0x000f in the entire memory
1558 for(i=0; i < j; i++)
1561 vcsize_sel = 0;
1567 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1570 for(i = 0; i < j; i++)
1587 memset ((char*)abr_vc_table, 0, j * sizeof(*abr_vc_table));
1588 for(i = 0; i < j; i++) {
1589 abr_vc_table->rdf = 0x0003;
1590 abr_vc_table->air = 0x5eb1;
1597 writew(0xff00, iadev->reass_reg+VP_FILTER);
1598 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1599 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1605 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1607 i = (j >> 6) & 0xFF;
1609 i |= ((j << 2) & 0xFF00);
1613 for(i=0; i<iadev->num_tx_desc;i++)
1614 iadev->desc_tbl[i].timestamp = 0;
1633 iadev->rx_pkt_cnt = 0;
1636 return 0;
1650 Buffer descr 0x0000 (128 - 4K)
1651 UBR sched 0x1000 (1K - 4K)
1652 UBR Wait q 0x2000 (1K - 4K)
1653 Commn queues 0x3000 Packet Ready, Trasmit comp(0x3100)
1655 extended VC 0x4000 (1K - 8K)
1656 ABR sched 0x6000 and ABR wait queue (1K - 2K) each
1657 CBR sched 0x7000 (as needed)
1658 VC table 0x8000 (1K - 32K)
1729 if ((vcc->pop) && (skb->len != 0))
1741 IF_EVENT(printk("tx_dle_intr: enque skb = 0x%p \n", skb);)
1757 if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
1771 memset((caddr_t)ia_vcc, 0, sizeof(*ia_vcc));
1780 ia_vcc->vc_desc_cnt = 0;
1786 else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))
1788 else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0))
1803 if (vcc->qos.txtp.max_sdu != 0) {
1819 memset((caddr_t)vc, 0, sizeof(*vc));
1820 memset((caddr_t)evc, 0, sizeof(*evc));
1827 evc->atm_hdr1 = (vcc->vci >> 12) & 0x000f;
1828 evc->atm_hdr2 = (vcc->vci & 0x0fff) << 4;
1836 if (vcc->qos.txtp.pcr > 0)
1838 IF_UBR(printk("UBR: txtp.pcr = 0x%x f_rate = 0x%x\n",
1845 if (vcc->qos.txtp.pcr > 0)
1847 if (vcc->qos.txtp.min_pcr > 0) {
1854 else srv_p.mcr = 0;
1889 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1898 return 0;
1921 IF_INIT(printk("Tx MASK REG: 0x%0x\n",
1937 writel(iadev->tx_dle_dma & 0xfffff000,
1939 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1940 writew(0, iadev->seg_reg+MODE_REG_0);
1949 Buffer descr 0x0000 (128 - 4K)
1950 Commn queues 0x1000 Transmit comp, Packet ready(0x1400)
1953 CBR Table 0x1800 (as needed) - 6K
1954 UBR Table 0x3000 (1K - 4K) - 12K
1955 UBR Wait queue 0x4000 (1K - 4K) - 16K
1956 ABR sched 0x5000 and ABR wait queue (1K - 2K) each
1958 extended VC 0x6000 (1K - 8K) - 24K
1959 VC Table 0x8000 (1K - 32K) - 32K
1961 Between 0x2000 (8K) and 0x3000 (12K) there is 4K space left for VBR Tbl
1970 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1975 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1978 buf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff;
1989 for (i= 0; i< iadev->num_tx_desc; i++)
2041 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2042 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2043 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2045 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2046 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2047 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2055 *prq_start = (u_short)0; /* desc 1 in all entries */
2060 #if 1 /* for 1K VC board, CBR_PTR_BASE is 0 */
2061 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2064 IF_INIT(printk("cbr_ptr_base = 0x%x ", tmp16);)
2068 IF_INIT(printk("value in register = 0x%x\n",
2072 IF_INIT(printk("cbr_tab_beg = 0x%x in reg = 0x%x \n", tmp16,
2077 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
2079 IF_INIT(printk("CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\n",
2085 0, iadev->num_vc*6);
2087 iadev->CbrEntryPt = 0;
2089 iadev->NumEnabledCBR = 0;
2092 /* initialize all bytes of UBR scheduler table and wait queue to 0
2100 vcsize_sel = 0;
2108 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2110 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2112 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2114 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2116 0, iadev->num_vc*8);
2117 /* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/
2118 /* initialize all bytes of ABR scheduler table and wait queue to 0
2126 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2128 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2131 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2141 for(i=0; i<iadev->num_vc; i++)
2143 memset((caddr_t)vc, 0, sizeof(*vc));
2144 memset((caddr_t)evc, 0, sizeof(*evc));
2149 iadev->testTable[i]->lastTime = 0;
2150 iadev->testTable[i]->fract = 0;
2161 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2165 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2168 writew(0, iadev->seg_reg+IDLEHEADHI);
2169 writew(0, iadev->seg_reg+IDLEHEADLO);
2172 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2174 iadev->close_pending = 0;
2187 /* Mode Register 0 */
2196 iadev->tx_pkt_cnt = 0;
2199 return 0;
2202 while (--i >= 0)
2210 while (--i >= 0) {
2230 int handled = 0;
2234 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2237 IF_EVENT(printk("ia_int: status = 0x%x\n", status);)
2284 IF_INIT(printk("ESI: 0x%08x%04x\n", mac1, mac2);)
2285 for (i=0; i<MAC1_LEN; i++)
2288 for (i=0; i<MAC2_LEN; i++)
2290 return 0;
2300 for(i=0; i<64; i++)
2304 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2305 for(i=0; i<64; i++)
2310 return 0;
2327 dev->ci_range.vpi_bits = 0;
2331 real_base = pci_resource_start (iadev->pci, 0);
2336 printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
2340 IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
2345 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2347 if (iadev->pci_map_size == 0x100000){
2352 else if (iadev->pci_map_size == 0x40000) {
2357 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2414 for (i=0; i < ESI_LEN; i++)
2424 return 0;
2430 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2431 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2432 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2433 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2434 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2435 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2441 static u_char blinking[8] = {0, 0, 0, 0, 0, 0, 0, 0};
2444 for (i = 0; i < iadev_count; i++) {
2447 if (blinking[i] == 0) {
2454 blinking[i] = 0;
2485 for (i = 0; i < iadev->num_vc; i++)
2488 for (i = 0; i < iadev->num_tx_desc; i++) {
2528 "master (0x%x)\n",dev->number, error);
2574 phy = 0; /* resolve compiler complaint */
2576 if ((phy=ia_phy_get(dev,0)) == 0x30)
2577 printk("IA: pm5346,rev.%d\n",phy&0x0f);
2579 printk("IA: utopia,rev.%0x\n",phy);)
2597 return 0;
2646 if (closetime == 0)
2649 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2652 iadev->testTable[vcc->vci]->lastTime = 0;
2653 iadev->testTable[vcc->vci]->fract = 0;
2656 if (vcc->qos.txtp.min_pcr > 0)
2680 abr_vc_table->rdf = 0x0003;
2681 abr_vc_table->air = 0x5eb1;
2734 #if 0
2740 first = 0;
2745 return 0;
2751 return 0;
2768 if ((board < 0) || (board > iadev_count))
2769 board = 0;
2780 for(i=0; i<0x80; i+=2, tmps++)
2781 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2782 ia_cmds.status = 0;
2783 ia_cmds.len = 0x80;
2788 for(i=0; i<0x80; i+=2, tmps++)
2789 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2790 ia_cmds.status = 0;
2791 ia_cmds.len = 0x80;
2805 for (i=0; i<(sizeof (rfredn_t))/4; i++)
2806 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2808 for (i=0; i<(sizeof (ffredn_t))/4; i++)
2809 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2817 ia_cmds.status = 0;
2824 ia_cmds.status = 0;
2827 case 0x6:
2829 ia_cmds.status = 0;
2830 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2831 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2834 case 0x8:
2848 ia_cmds.status = 0;
2850 case 0x9:
2858 ia_cmds.status = 0;
2861 case 0xb:
2865 case 0xa:
2868 ia_cmds.status = 0;
2874 ia_cmds.status = 0;
2883 return 0;
2904 return 0;
2913 return 0;
2921 return 0;
2929 if (desc == 0xffff)
2932 desc &= 0x1fff;
2934 if ((desc == 0) || (desc > iadev->num_tx_desc))
2942 return 0; /* return SUCCESS */
2955 IA_SKB_STATE(skb) = 0;
2979 IF_TX(printk("Sent: skb = 0x%p skb->data: 0x%p len: %d, desc: %d\n",
2981 trailer->control = 0;
2983 trailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);
2984 trailer->crc32 = 0; /* not needed - dummy bytes */
3006 memset((caddr_t)wr_ptr, 0, sizeof(*wr_ptr));
3014 /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */
3015 if ((wr_ptr->bytes >> 2) == 0xb)
3016 wr_ptr->bytes = 0x30;
3019 wr_ptr->prq_wr_ptr_data = 0;
3047 #if 0
3049 if (atomic_read(&vcc->stats->tx) % 20 == 0) {
3055 } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {
3058 iavcc->flow_inc = 0;
3063 return 0;
3096 return 0;
3119 if (iadev->pci_map_size == 0x40000)
3149 return 0;
3191 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3212 return 0;
3255 { PCI_VENDOR_ID_IPHASE, 0x0008, PCI_ANY_ID, PCI_ANY_ID, },
3256 { PCI_VENDOR_ID_IPHASE, 0x0009, PCI_ANY_ID, PCI_ANY_ID, },
3257 { 0,}
3273 if (ret >= 0) {