Lines Matching +full:fis +full:- +full:index +full:- +full:block
1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
47 #include <linux/dma-mapping.h>
95 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
97 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
103 * Per-chip ("all ports") interrupt coalescing feature.
133 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
147 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
148 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
164 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
165 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
166 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
172 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
173 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
203 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
209 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
216 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
217 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
230 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
231 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
242 * Per-HC (Host-Controller) interrupt coalescing feature.
256 /* Shadow block registers */
266 LTMODE = 0x30c, /* requires read-after-write */
272 PHY_MODE4 = 0x314, /* requires read-after-write */
311 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
312 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
322 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
323 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
324 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
335 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
344 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
397 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
425 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
449 * we need on /length/ in mv_fill-sg().
473 /* Command ReQuest Block: 32B */
489 /* Command ResPonse Block: 8B */
507 * when switching between EDMA and non-EDMA modes.
556 * all the clock operations become no-ops (see clk.h).
568 * alignment for hardware-accessed data structures,
670 .can_queue = MV_MAX_Q_DEPTH - 1,
878 * This is hot-path stuff, so not a function.
922 struct mv_host_priv *hpriv = host->private_data; in mv_host_base()
923 return hpriv->base; in mv_host_base()
928 return mv_port_base(mv_host_base(ap->host), ap->port_no); in mv_ap_base()
937 * mv_save_cached_regs - (re-)initialize cached port registers
949 struct mv_port_priv *pp = ap->private_data; in mv_save_cached_regs()
951 pp->cached.fiscfg = readl(port_mmio + FISCFG); in mv_save_cached_regs()
952 pp->cached.ltmode = readl(port_mmio + LTMODE); in mv_save_cached_regs()
953 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); in mv_save_cached_regs()
954 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); in mv_save_cached_regs()
958 * mv_write_cached_reg - write to a cached port register
972 * Workaround for 88SX60x1-B2 FEr SATA#13: in mv_write_cached_reg()
973 * Read-after-write is needed to prevent generating 64-bit in mv_write_cached_reg()
978 * +1 usec read-after-write delay for unaffected registers. in mv_write_cached_reg()
996 u32 index; in mv_set_edma_ptrs() local
1001 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
1002 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1004 WARN_ON(pp->crqb_dma & 0x3ff); in mv_set_edma_ptrs()
1005 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); in mv_set_edma_ptrs()
1006 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1008 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); in mv_set_edma_ptrs()
1013 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
1014 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1016 WARN_ON(pp->crpb_dma & 0xff); in mv_set_edma_ptrs()
1017 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); in mv_set_edma_ptrs()
1018 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); in mv_set_edma_ptrs()
1019 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1037 writelfl(mask, hpriv->main_irq_mask_addr); in mv_write_main_irq_mask()
1043 struct mv_host_priv *hpriv = host->private_data; in mv_set_main_irq_mask()
1046 old_mask = hpriv->main_irq_mask; in mv_set_main_irq_mask()
1049 hpriv->main_irq_mask = new_mask; in mv_set_main_irq_mask()
1057 unsigned int shift, hardport, port = ap->port_no; in mv_enable_port_irqs()
1064 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); in mv_enable_port_irqs()
1071 struct mv_host_priv *hpriv = ap->host->private_data; in mv_clear_and_enable_port_irqs()
1072 int hardport = mv_hardport_from_port(ap->port_no); in mv_clear_and_enable_port_irqs()
1074 mv_host_base(ap->host), ap->port_no); in mv_clear_and_enable_port_irqs()
1084 /* clear FIS IRQ Cause */ in mv_clear_and_enable_port_irqs()
1094 struct mv_host_priv *hpriv = host->private_data; in mv_set_irq_coalescing()
1095 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_set_irq_coalescing()
1098 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; in mv_set_irq_coalescing()
1114 spin_lock_irqsave(&host->lock, flags); in mv_set_irq_coalescing()
1150 spin_unlock_irqrestore(&host->lock, flags); in mv_set_irq_coalescing()
1154 * mv_start_edma - Enable eDMA engine
1168 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { in mv_start_edma()
1169 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); in mv_start_edma()
1173 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { in mv_start_edma()
1174 struct mv_host_priv *hpriv = ap->host->private_data; in mv_start_edma()
1182 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; in mv_start_edma()
1197 * with two drives in-use. So we use the 15msec value above in mv_wait_for_edma_empty_idle()
1210 * mv_stop_edma_engine - Disable eDMA engine
1224 for (i = 10000; i > 0; i--) { in mv_stop_edma_engine()
1230 return -EIO; in mv_stop_edma_engine()
1236 struct mv_port_priv *pp = ap->private_data; in mv_stop_edma()
1239 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_stop_edma()
1241 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_stop_edma()
1245 err = -EIO; in mv_stop_edma()
1301 DPRINTK("All registers for port(s) %u-%u:\n", start_port, in mv_dump_all_regs()
1302 num_ports > 1 ? num_ports - 1 : start_port); in mv_dump_all_regs()
1353 *val = readl(mv_ap_base(link->ap) + ofs); in mv_scr_read()
1356 return -EINVAL; in mv_scr_read()
1364 void __iomem *addr = mv_ap_base(link->ap) + ofs; in mv_scr_write()
1365 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv_scr_write()
1383 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { in mv_scr_write()
1385 mv_ap_base(link->ap) + LP_PHY_CTL; in mv_scr_write()
1405 return -EINVAL; in mv_scr_write()
1411 * Deal with Gen-II ("mv6") hardware quirks/restrictions: in mv6_dev_config()
1413 * Gen-II does not support NCQ over a port multiplier in mv6_dev_config()
1414 * (no FIS-based switching). in mv6_dev_config()
1416 if (adev->flags & ATA_DFLAG_NCQ) { in mv6_dev_config()
1417 if (sata_pmp_attached(adev->link->ap)) { in mv6_dev_config()
1418 adev->flags &= ~ATA_DFLAG_NCQ; in mv6_dev_config()
1420 "NCQ disabled for command-based switching\n"); in mv6_dev_config()
1427 struct ata_link *link = qc->dev->link; in mv_qc_defer()
1428 struct ata_port *ap = link->ap; in mv_qc_defer()
1429 struct mv_port_priv *pp = ap->private_data; in mv_qc_defer()
1433 * for NCQ and/or FIS-based switching. in mv_qc_defer()
1435 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_qc_defer()
1441 * or a non-NCQ command in NCQ mode. in mv_qc_defer()
1446 if (unlikely(ap->excl_link)) { in mv_qc_defer()
1447 if (link == ap->excl_link) { in mv_qc_defer()
1448 if (ap->nr_active_links) in mv_qc_defer()
1450 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; in mv_qc_defer()
1459 if (ap->nr_active_links == 0) in mv_qc_defer()
1468 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && in mv_qc_defer()
1469 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { in mv_qc_defer()
1470 if (ata_is_ncq(qc->tf.protocol)) in mv_qc_defer()
1473 ap->excl_link = link; in mv_qc_defer()
1483 struct mv_port_priv *pp = ap->private_data; in mv_config_fbs()
1486 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; in mv_config_fbs()
1487 u32 ltmode, *old_ltmode = &pp->cached.ltmode; in mv_config_fbs()
1488 u32 haltcond, *old_haltcond = &pp->cached.haltcond; in mv_config_fbs()
1512 struct mv_host_priv *hpriv = ap->host->private_data; in mv_60x1_errata_sata25()
1516 old = readl(hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1522 writel(new, hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1526 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1531 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1539 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_enable_iie()
1540 u32 new, *old = &pp->cached.unknown_rsvd; in mv_bmdma_enable_iie()
1565 struct ata_host *host = ap->host; in mv_soc_led_blink_enable()
1566 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_enable()
1570 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) in mv_soc_led_blink_enable()
1572 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_enable()
1573 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_enable()
1580 struct ata_host *host = ap->host; in mv_soc_led_blink_disable()
1581 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_disable()
1586 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) in mv_soc_led_blink_disable()
1589 /* disable led-blink only if no ports are using NCQ */ in mv_soc_led_blink_disable()
1590 for (port = 0; port < hpriv->n_ports; port++) { in mv_soc_led_blink_disable()
1591 struct ata_port *this_ap = host->ports[port]; in mv_soc_led_blink_disable()
1592 struct mv_port_priv *pp = this_ap->private_data; in mv_soc_led_blink_disable()
1594 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_soc_led_blink_disable()
1598 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_disable()
1599 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_disable()
1607 struct mv_port_priv *pp = ap->private_data; in mv_edma_cfg()
1608 struct mv_host_priv *hpriv = ap->host->private_data; in mv_edma_cfg()
1611 /* set up non-NCQ EDMA configuration */ in mv_edma_cfg()
1613 pp->pp_flags &= in mv_edma_cfg()
1628 * The chip can use FBS with non-NCQ, if we allow it, in mv_edma_cfg()
1631 * So disallow non-NCQ FBS for now. in mv_edma_cfg()
1638 pp->pp_flags |= MV_PP_FLAG_FBS_EN; in mv_edma_cfg()
1639 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ in mv_edma_cfg()
1642 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ in mv_edma_cfg()
1644 cfg |= (1 << 22); /* enab 4-entry host queue cache */ in mv_edma_cfg()
1648 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) in mv_edma_cfg()
1649 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ in mv_edma_cfg()
1662 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; in mv_edma_cfg()
1670 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_free_dma_mem()
1671 struct mv_port_priv *pp = ap->private_data; in mv_port_free_dma_mem()
1674 if (pp->crqb) { in mv_port_free_dma_mem()
1675 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); in mv_port_free_dma_mem()
1676 pp->crqb = NULL; in mv_port_free_dma_mem()
1678 if (pp->crpb) { in mv_port_free_dma_mem()
1679 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); in mv_port_free_dma_mem()
1680 pp->crpb = NULL; in mv_port_free_dma_mem()
1687 if (pp->sg_tbl[tag]) { in mv_port_free_dma_mem()
1689 dma_pool_free(hpriv->sg_tbl_pool, in mv_port_free_dma_mem()
1690 pp->sg_tbl[tag], in mv_port_free_dma_mem()
1691 pp->sg_tbl_dma[tag]); in mv_port_free_dma_mem()
1692 pp->sg_tbl[tag] = NULL; in mv_port_free_dma_mem()
1698 * mv_port_start - Port specific init/start routine.
1709 struct device *dev = ap->host->dev; in mv_port_start()
1710 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_start()
1717 return -ENOMEM; in mv_port_start()
1718 ap->private_data = pp; in mv_port_start()
1720 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); in mv_port_start()
1721 if (!pp->crqb) in mv_port_start()
1722 return -ENOMEM; in mv_port_start()
1724 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); in mv_port_start()
1725 if (!pp->crpb) in mv_port_start()
1729 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) in mv_port_start()
1730 ap->flags |= ATA_FLAG_AN; in mv_port_start()
1737 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, in mv_port_start()
1738 GFP_KERNEL, &pp->sg_tbl_dma[tag]); in mv_port_start()
1739 if (!pp->sg_tbl[tag]) in mv_port_start()
1742 pp->sg_tbl[tag] = pp->sg_tbl[0]; in mv_port_start()
1743 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; in mv_port_start()
1747 spin_lock_irqsave(ap->lock, flags); in mv_port_start()
1750 spin_unlock_irqrestore(ap->lock, flags); in mv_port_start()
1756 return -ENOMEM; in mv_port_start()
1760 * mv_port_stop - Port specific cleanup/stop routine.
1772 spin_lock_irqsave(ap->lock, flags); in mv_port_stop()
1775 spin_unlock_irqrestore(ap->lock, flags); in mv_port_stop()
1780 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1790 struct mv_port_priv *pp = qc->ap->private_data; in mv_fill_sg()
1795 mv_sg = pp->sg_tbl[qc->hw_tag]; in mv_fill_sg()
1796 for_each_sg(qc->sg, sg, qc->n_elem, si) { in mv_fill_sg()
1805 len = 0x10000 - offset; in mv_fill_sg()
1807 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); in mv_fill_sg()
1808 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); in mv_fill_sg()
1809 mv_sg->flags_size = cpu_to_le32(len & 0xffff); in mv_fill_sg()
1810 mv_sg->reserved = 0; in mv_fill_sg()
1812 sg_len -= len; in mv_fill_sg()
1821 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); in mv_fill_sg()
1833 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1838 * after libata-sff handles the bmdma interrupts.
1846 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1858 struct scsi_cmnd *scmd = qc->scsicmd; in mv_check_atapi_dma()
1861 switch (scmd->cmnd[0]) { in mv_check_atapi_dma()
1874 return -EOPNOTSUPP; /* use PIO instead */ in mv_check_atapi_dma()
1878 * mv_bmdma_setup - Set up BMDMA transaction
1886 struct ata_port *ap = qc->ap; in mv_bmdma_setup()
1888 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_setup()
1896 writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16, in mv_bmdma_setup()
1898 writelfl(pp->sg_tbl_dma[qc->hw_tag], in mv_bmdma_setup()
1902 ap->ops->sff_exec_command(ap, &qc->tf); in mv_bmdma_setup()
1906 * mv_bmdma_start - Start a BMDMA transaction
1914 struct ata_port *ap = qc->ap; in mv_bmdma_start()
1916 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); in mv_bmdma_start()
1924 * mv_bmdma_stop_ap - Stop BMDMA transfer
1943 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ in mv_bmdma_stop_ap()
1950 mv_bmdma_stop_ap(qc->ap); in mv_bmdma_stop()
1954 * mv_bmdma_status - Read BMDMA status
1984 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) in mv_bmdma_status()
1994 struct ata_taskfile *tf = &qc->tf; in mv_rw_multi_errata_sata24()
2008 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { in mv_rw_multi_errata_sata24()
2009 if (qc->dev->multi_count > 7) { in mv_rw_multi_errata_sata24()
2010 switch (tf->command) { in mv_rw_multi_errata_sata24()
2012 tf->command = ATA_CMD_PIO_WRITE; in mv_rw_multi_errata_sata24()
2015 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ in mv_rw_multi_errata_sata24()
2018 tf->command = ATA_CMD_PIO_WRITE_EXT; in mv_rw_multi_errata_sata24()
2026 * mv_qc_prep - Host specific command preparation.
2031 * (command request block), does some sanity checking, and calls
2039 struct ata_port *ap = qc->ap; in mv_qc_prep()
2040 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep()
2042 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep()
2046 switch (tf->protocol) { in mv_qc_prep()
2048 if (tf->command == ATA_CMD_DSM) in mv_qc_prep()
2060 /* Fill in command request block in mv_qc_prep()
2062 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep()
2064 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep()
2065 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep()
2066 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep()
2068 /* get current queue index from software */ in mv_qc_prep()
2069 in_index = pp->req_idx; in mv_qc_prep()
2071 pp->crqb[in_index].sg_addr = in mv_qc_prep()
2072 cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep()
2073 pp->crqb[in_index].sg_addr_hi = in mv_qc_prep()
2074 cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep()
2075 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); in mv_qc_prep()
2077 cw = &pp->crqb[in_index].ata_cmd[0]; in mv_qc_prep()
2079 /* Sadly, the CRQB cannot accommodate all registers--there are in mv_qc_prep()
2086 switch (tf->command) { in mv_qc_prep()
2092 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2096 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2097 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2100 /* The only other commands EDMA supports in non-queued and in mv_qc_prep()
2101 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none in mv_qc_prep()
2106 tf->command); in mv_qc_prep()
2109 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2110 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2111 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2112 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2113 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2114 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2115 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2116 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); in mv_qc_prep()
2117 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ in mv_qc_prep()
2119 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep()
2127 * mv_qc_prep_iie - Host specific command preparation.
2132 * (command request block), does some sanity checking, and calls
2140 struct ata_port *ap = qc->ap; in mv_qc_prep_iie()
2141 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep_iie()
2143 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep_iie()
2147 if ((tf->protocol != ATA_PROT_DMA) && in mv_qc_prep_iie()
2148 (tf->protocol != ATA_PROT_NCQ)) in mv_qc_prep_iie()
2150 if (tf->command == ATA_CMD_DSM) in mv_qc_prep_iie()
2153 /* Fill in Gen IIE command request block */ in mv_qc_prep_iie()
2154 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep_iie()
2157 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep_iie()
2158 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep_iie()
2159 flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT; in mv_qc_prep_iie()
2160 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep_iie()
2162 /* get current queue index from software */ in mv_qc_prep_iie()
2163 in_index = pp->req_idx; in mv_qc_prep_iie()
2165 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; in mv_qc_prep_iie()
2166 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep_iie()
2167 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep_iie()
2168 crqb->flags = cpu_to_le32(flags); in mv_qc_prep_iie()
2170 crqb->ata_cmd[0] = cpu_to_le32( in mv_qc_prep_iie()
2171 (tf->command << 16) | in mv_qc_prep_iie()
2172 (tf->feature << 24) in mv_qc_prep_iie()
2174 crqb->ata_cmd[1] = cpu_to_le32( in mv_qc_prep_iie()
2175 (tf->lbal << 0) | in mv_qc_prep_iie()
2176 (tf->lbam << 8) | in mv_qc_prep_iie()
2177 (tf->lbah << 16) | in mv_qc_prep_iie()
2178 (tf->device << 24) in mv_qc_prep_iie()
2180 crqb->ata_cmd[2] = cpu_to_le32( in mv_qc_prep_iie()
2181 (tf->hob_lbal << 0) | in mv_qc_prep_iie()
2182 (tf->hob_lbam << 8) | in mv_qc_prep_iie()
2183 (tf->hob_lbah << 16) | in mv_qc_prep_iie()
2184 (tf->hob_feature << 24) in mv_qc_prep_iie()
2186 crqb->ata_cmd[3] = cpu_to_le32( in mv_qc_prep_iie()
2187 (tf->nsect << 0) | in mv_qc_prep_iie()
2188 (tf->hob_nsect << 8) in mv_qc_prep_iie()
2191 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep_iie()
2199 * mv_sff_check_status - fetch device status, if valid
2213 u8 stat = ioread8(ap->ioaddr.status_addr); in mv_sff_check_status()
2214 struct mv_port_priv *pp = ap->private_data; in mv_sff_check_status()
2216 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { in mv_sff_check_status()
2218 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; in mv_sff_check_status()
2226 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2227 * @ap: ATA port to send a FIS
2228 * @fis: fis to be sent
2229 * @nwords: number of 32-bit words in the fis
2231 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) in mv_send_fis() argument
2235 int i, timeout = 200, final_word = nwords - 1; in mv_send_fis()
2237 /* Initiate FIS transmission mode */ in mv_send_fis()
2242 /* Send all words of the FIS except for the final word */ in mv_send_fis()
2244 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); in mv_send_fis()
2246 /* Flag end-of-transmission, and then send the final word */ in mv_send_fis()
2248 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); in mv_send_fis()
2251 * Wait for FIS transmission to complete. in mv_send_fis()
2256 } while (!(ifstat & 0x1000) && --timeout); in mv_send_fis()
2271 * mv_qc_issue_fis - Issue a command directly as a FIS
2281 * of non-data commands. So avoid sending them via this function,
2289 struct ata_port *ap = qc->ap; in mv_qc_issue_fis()
2290 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue_fis()
2291 struct ata_link *link = qc->dev->link; in mv_qc_issue_fis()
2292 u32 fis[5]; in mv_qc_issue_fis() local
2295 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); in mv_qc_issue_fis()
2296 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); in mv_qc_issue_fis()
2300 switch (qc->tf.protocol) { in mv_qc_issue_fis()
2302 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2305 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2308 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2309 if (qc->tf.flags & ATA_TFLAG_WRITE) in mv_qc_issue_fis()
2310 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2312 ap->hsm_task_state = HSM_ST; in mv_qc_issue_fis()
2315 ap->hsm_task_state = HSM_ST_LAST; in mv_qc_issue_fis()
2319 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue_fis()
2325 * mv_qc_issue - Initiate a command to the host
2331 * DMA and bumps the request producer index.
2339 struct ata_port *ap = qc->ap; in mv_qc_issue()
2341 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue()
2345 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ in mv_qc_issue()
2347 switch (qc->tf.protocol) { in mv_qc_issue()
2349 if (qc->tf.command == ATA_CMD_DSM) { in mv_qc_issue()
2350 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ in mv_qc_issue()
2356 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); in mv_qc_issue()
2357 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_qc_issue()
2358 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_qc_issue()
2361 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, in mv_qc_issue()
2372 * than a single block of data. in mv_qc_issue()
2377 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { in mv_qc_issue()
2378 --limit_warnings; in mv_qc_issue()
2379 ata_link_warn(qc->dev->link, DRV_NAME in mv_qc_issue()
2387 if (ap->flags & ATA_FLAG_PIO_POLLING) in mv_qc_issue()
2388 qc->tf.flags |= ATA_TFLAG_POLLING; in mv_qc_issue()
2392 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue()
2398 * We're about to send a non-EDMA capable command to the in mv_qc_issue()
2400 * shadow block, etc registers. in mv_qc_issue()
2404 mv_pmp_select(ap, qc->dev->link->pmp); in mv_qc_issue()
2406 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { in mv_qc_issue()
2407 struct mv_host_priv *hpriv = ap->host->private_data; in mv_qc_issue()
2412 * from libata-eh *must* use mv_qc_issue_fis(). in mv_qc_issue()
2415 * Rather than special-case it, we'll just *always* in mv_qc_issue()
2427 struct mv_port_priv *pp = ap->private_data; in mv_get_active_qc()
2430 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_get_active_qc()
2432 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_get_active_qc()
2433 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) in mv_get_active_qc()
2441 struct mv_port_priv *pp = ap->private_data; in mv_pmp_error_handler()
2443 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { in mv_pmp_error_handler()
2450 pmp_map = pp->delayed_eh_pmp_map; in mv_pmp_error_handler()
2451 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; in mv_pmp_error_handler()
2455 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_error_handler()
2482 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_eh_prep()
2483 struct ata_eh_info *ehi = &link->eh_info; in mv_pmp_eh_prep()
2488 ehi->err_mask |= AC_ERR_DEV; in mv_pmp_eh_prep()
2489 ehi->action |= ATA_EH_RESET; in mv_pmp_eh_prep()
2509 struct mv_port_priv *pp = ap->private_data; in mv_handle_fbs_ncq_dev_err()
2518 * Perform the post-mortem/EH only when all responses are complete. in mv_handle_fbs_ncq_dev_err()
2521 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { in mv_handle_fbs_ncq_dev_err()
2522 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; in mv_handle_fbs_ncq_dev_err()
2523 pp->delayed_eh_pmp_map = 0; in mv_handle_fbs_ncq_dev_err()
2525 old_map = pp->delayed_eh_pmp_map; in mv_handle_fbs_ncq_dev_err()
2529 pp->delayed_eh_pmp_map = new_map; in mv_handle_fbs_ncq_dev_err()
2536 __func__, pp->delayed_eh_pmp_map, in mv_handle_fbs_ncq_dev_err()
2537 ap->qc_active, failed_links, in mv_handle_fbs_ncq_dev_err()
2538 ap->nr_active_links); in mv_handle_fbs_ncq_dev_err()
2540 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { in mv_handle_fbs_ncq_dev_err()
2556 * FBS+non-NCQ operation is not yet implemented. in mv_handle_fbs_non_ncq_dev_err()
2559 * Device error during FBS+non-NCQ operation: in mv_handle_fbs_non_ncq_dev_err()
2569 struct mv_port_priv *pp = ap->private_data; in mv_handle_dev_err()
2571 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_handle_dev_err()
2573 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) in mv_handle_dev_err()
2582 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { in mv_handle_dev_err()
2584 * EDMA should NOT have self-disabled for this case. in mv_handle_dev_err()
2590 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2596 * EDMA should have self-disabled for this case. in mv_handle_dev_err()
2602 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2612 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_unexpected_intr()
2619 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_unexpected_intr()
2620 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) in mv_unexpected_intr()
2624 ehi->err_mask |= AC_ERR_OTHER; in mv_unexpected_intr()
2625 ehi->action |= ATA_EH_RESET; in mv_unexpected_intr()
2630 * mv_err_intr - Handle error interrupts on the port
2645 struct mv_port_priv *pp = ap->private_data; in mv_err_intr()
2646 struct mv_host_priv *hpriv = ap->host->private_data; in mv_err_intr()
2648 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_err_intr()
2657 sata_scr_read(&ap->link, SCR_ERROR, &serr); in mv_err_intr()
2658 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); in mv_err_intr()
2669 * Device errors during FIS-based switching operation in mv_err_intr()
2679 edma_err_cause, pp->pp_flags); in mv_err_intr()
2715 * Gen-I has a different SELF_DIS bit, in mv_err_intr()
2721 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2722 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2727 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2728 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2742 ehi->serror |= serr; in mv_err_intr()
2743 ehi->action |= action; in mv_err_intr()
2746 qc->err_mask |= err_mask; in mv_err_intr()
2748 ehi->err_mask |= err_mask; in mv_err_intr()
2769 ata_link_abort(qc->dev->link); in mv_err_intr()
2779 u16 edma_status = le16_to_cpu(response->flags); in mv_process_crpb_response()
2783 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). in mv_process_crpb_response()
2806 struct mv_host_priv *hpriv = ap->host->private_data; in mv_process_crpb_entries()
2810 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); in mv_process_crpb_entries()
2812 /* Get the hardware queue position index */ in mv_process_crpb_entries()
2817 while (in_index != pp->resp_idx) { in mv_process_crpb_entries()
2819 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; in mv_process_crpb_entries()
2821 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_process_crpb_entries()
2825 tag = ap->link.active_tag; in mv_process_crpb_entries()
2828 tag = le16_to_cpu(response->id) & 0x1f; in mv_process_crpb_entries()
2838 /* Update the software queue position index in hardware */ in mv_process_crpb_entries()
2839 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | in mv_process_crpb_entries()
2840 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), in mv_process_crpb_entries()
2855 pp = ap->private_data; in mv_port_intr()
2856 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); in mv_port_intr()
2862 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_port_intr()
2866 * Handle chip-reported errors, or continue on to handle PIO. in mv_port_intr()
2880 * mv_host_intr - Handle all interrupts on the given host controller
2889 struct mv_host_priv *hpriv = host->private_data; in mv_host_intr()
2890 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_host_intr()
2897 for (port = 0; port < hpriv->n_ports; port++) { in mv_host_intr()
2898 struct ata_port *ap = host->ports[port]; in mv_host_intr()
2913 port += MV_PORTS_PER_HC - 1; in mv_host_intr()
2932 if ((port + p) >= hpriv->n_ports) in mv_host_intr()
2954 struct mv_host_priv *hpriv = host->private_data; in mv_pci_error()
2961 err_cause = readl(mmio + hpriv->irq_cause_offset); in mv_pci_error()
2963 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); in mv_pci_error()
2966 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); in mv_pci_error()
2968 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_pci_error()
2970 for (i = 0; i < host->n_ports; i++) { in mv_pci_error()
2971 ap = host->ports[i]; in mv_pci_error()
2972 if (!ata_link_offline(&ap->link)) { in mv_pci_error()
2973 ehi = &ap->link.eh_info; in mv_pci_error()
2979 ehi->action = ATA_EH_RESET; in mv_pci_error()
2980 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_pci_error()
2982 qc->err_mask |= err_mask; in mv_pci_error()
2984 ehi->err_mask |= err_mask; in mv_pci_error()
2993 * mv_interrupt - Main interrupt event handler
3009 struct mv_host_priv *hpriv = host->private_data; in mv_interrupt()
3011 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; in mv_interrupt()
3014 spin_lock(&host->lock); in mv_interrupt()
3016 /* for MSI: block new interrupts while in here */ in mv_interrupt()
3020 main_irq_cause = readl(hpriv->main_irq_cause_addr); in mv_interrupt()
3021 pending_irqs = main_irq_cause & hpriv->main_irq_mask; in mv_interrupt()
3028 handled = mv_pci_error(host, hpriv->base); in mv_interrupt()
3035 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); in mv_interrupt()
3037 spin_unlock(&host->lock); in mv_interrupt()
3061 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_read()
3062 void __iomem *mmio = hpriv->base; in mv5_scr_read()
3063 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_read()
3070 return -EINVAL; in mv5_scr_read()
3075 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_write()
3076 void __iomem *mmio = hpriv->base; in mv5_scr_write()
3077 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_write()
3084 return -EINVAL; in mv5_scr_write()
3089 struct pci_dev *pdev = to_pci_dev(host->dev); in mv5_reset_bus()
3092 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); in mv5_reset_bus()
3116 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ in mv5_read_preamp()
3117 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ in mv5_read_preamp()
3139 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); in mv5_phy_errata()
3154 tmp |= hpriv->signal[port].pre; in mv5_phy_errata()
3155 tmp |= hpriv->signal[port].amps; in mv5_phy_errata()
3224 struct mv_host_priv *hpriv = host->private_data; in mv_reset_pci_bus()
3235 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3236 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3257 * mv6_reset_hc - Perform the 6xxx global soft reset
3296 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3310 } while ((GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3328 hpriv->signal[idx].amps = 0x7 << 8; in mv6_read_preamp()
3329 hpriv->signal[idx].pre = 0x1 << 5; in mv6_read_preamp()
3336 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv6_read_preamp()
3337 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv6_read_preamp()
3350 u32 hp_flags = hpriv->hp_flags; in mv6_phy_errata()
3373 * Gen-II/IIe PHY_MODE3 errata RM#2: in mv6_phy_errata()
3379 /* Guideline 88F5182 (GL# SATA-S11) */ in mv6_phy_errata()
3386 * Enforce reserved-bit restrictions on GenIIe devices only. in mv6_phy_errata()
3397 * Workaround for 60x1-B2 errata SATA#13: in mv6_phy_errata()
3404 /* Revert values of pre-emphasis and signal amps to the saved ones */ in mv6_phy_errata()
3408 m2 |= hpriv->signal[port].amps; in mv6_phy_errata()
3409 m2 |= hpriv->signal[port].pre; in mv6_phy_errata()
3438 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv_soc_read_preamp()
3439 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv_soc_read_preamp()
3487 for (port = 0; port < hpriv->n_ports; port++) in mv_soc_reset_hc()
3538 * soc_is_65 - check if the soc is 65 nano device
3541 * register, this register should contain non-zero value and it exists only
3546 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); in soc_is_65n()
3589 hpriv->ops->phy_errata(hpriv, mmio, port_no); in mv_reset_channel()
3612 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_pmp_hardreset()
3619 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_softreset()
3626 struct ata_port *ap = link->ap; in mv_hardreset()
3627 struct mv_host_priv *hpriv = ap->host->private_data; in mv_hardreset()
3628 struct mv_port_priv *pp = ap->private_data; in mv_hardreset()
3629 void __iomem *mmio = hpriv->base; in mv_hardreset()
3634 mv_reset_channel(hpriv, mmio, ap->port_no); in mv_hardreset()
3635 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_hardreset()
3636 pp->pp_flags &= in mv_hardreset()
3642 sata_ehc_deb_timing(&link->eh_context); in mv_hardreset()
3646 rc = online ? -EAGAIN : rc; in mv_hardreset()
3671 struct mv_host_priv *hpriv = ap->host->private_data; in mv_eh_thaw()
3672 unsigned int port = ap->port_no; in mv_eh_thaw()
3674 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); in mv_eh_thaw()
3689 * mv_port_init - Perform some early initialization on a single port.
3706 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); in mv_port_init()
3707 port->error_addr = in mv_port_init()
3708 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); in mv_port_init()
3709 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); in mv_port_init()
3710 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); in mv_port_init()
3711 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); in mv_port_init()
3712 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); in mv_port_init()
3713 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); in mv_port_init()
3714 port->status_addr = in mv_port_init()
3715 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); in mv_port_init()
3717 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; in mv_port_init()
3724 /* unmask all non-transient EDMA error interrupts */ in mv_port_init()
3735 struct mv_host_priv *hpriv = host->private_data; in mv_in_pcix_mode()
3736 void __iomem *mmio = hpriv->base; in mv_in_pcix_mode()
3740 return 0; /* not PCI-X capable */ in mv_in_pcix_mode()
3744 return 1; /* chip is in PCI-X mode */ in mv_in_pcix_mode()
3749 struct mv_host_priv *hpriv = host->private_data; in mv_pci_cut_through_okay()
3750 void __iomem *mmio = hpriv->base; in mv_pci_cut_through_okay()
3763 struct mv_host_priv *hpriv = host->private_data; in mv_60x1b2_errata_pci7()
3764 void __iomem *mmio = hpriv->base; in mv_60x1b2_errata_pci7()
3766 /* workaround for 60x1-B2 errata PCI#7 */ in mv_60x1b2_errata_pci7()
3775 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_chip_id()
3776 struct mv_host_priv *hpriv = host->private_data; in mv_chip_id()
3777 u32 hp_flags = hpriv->hp_flags; in mv_chip_id()
3781 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3784 switch (pdev->revision) { in mv_chip_id()
3792 dev_warn(&pdev->dev, in mv_chip_id()
3801 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3804 switch (pdev->revision) { in mv_chip_id()
3812 dev_warn(&pdev->dev, in mv_chip_id()
3821 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3824 switch (pdev->revision) { in mv_chip_id()
3833 dev_warn(&pdev->dev, in mv_chip_id()
3842 if (pdev->vendor == PCI_VENDOR_ID_TTI && in mv_chip_id()
3843 (pdev->device == 0x2300 || pdev->device == 0x2310)) in mv_chip_id()
3850 * a "Lgcy" metadata block prior to Linux boot. in mv_chip_id()
3858 * RAID metadata is at: (dev->n_sectors & ~0xfffff) in mv_chip_id()
3867 " use sectors 8-9 on \"Legacy\" drives," in mv_chip_id()
3873 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3878 switch (pdev->revision) { in mv_chip_id()
3883 dev_warn(&pdev->dev, in mv_chip_id()
3891 hpriv->ops = &mv_soc_65n_ops; in mv_chip_id()
3893 hpriv->ops = &mv_soc_ops; in mv_chip_id()
3899 dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx); in mv_chip_id()
3900 return -EINVAL; in mv_chip_id()
3903 hpriv->hp_flags = hp_flags; in mv_chip_id()
3905 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; in mv_chip_id()
3906 hpriv->irq_mask_offset = PCIE_IRQ_MASK; in mv_chip_id()
3907 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; in mv_chip_id()
3909 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; in mv_chip_id()
3910 hpriv->irq_mask_offset = PCI_IRQ_MASK; in mv_chip_id()
3911 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; in mv_chip_id()
3918 * mv_init_host - Perform some early initialization of the host.
3930 struct mv_host_priv *hpriv = host->private_data; in mv_init_host()
3931 void __iomem *mmio = hpriv->base; in mv_init_host()
3933 rc = mv_chip_id(host, hpriv->board_idx); in mv_init_host()
3938 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3939 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; in mv_init_host()
3941 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3942 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; in mv_init_host()
3946 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); in mv_init_host()
3951 n_hc = mv_get_hc_count(host->ports[0]->flags); in mv_init_host()
3953 for (port = 0; port < host->n_ports; port++) in mv_init_host()
3954 if (hpriv->ops->read_preamp) in mv_init_host()
3955 hpriv->ops->read_preamp(hpriv, port, mmio); in mv_init_host()
3957 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); in mv_init_host()
3961 hpriv->ops->reset_flash(hpriv, mmio); in mv_init_host()
3962 hpriv->ops->reset_bus(host, mmio); in mv_init_host()
3963 hpriv->ops->enable_leds(hpriv, mmio); in mv_init_host()
3965 for (port = 0; port < host->n_ports; port++) { in mv_init_host()
3966 struct ata_port *ap = host->ports[port]; in mv_init_host()
3969 mv_port_init(&ap->ioaddr, port_mmio); in mv_init_host()
3986 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_init_host()
3989 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); in mv_init_host()
3994 * The per-port interrupts get done later as ports are set up. in mv_init_host()
4005 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, in mv_create_dma_pools()
4007 if (!hpriv->crqb_pool) in mv_create_dma_pools()
4008 return -ENOMEM; in mv_create_dma_pools()
4010 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, in mv_create_dma_pools()
4012 if (!hpriv->crpb_pool) in mv_create_dma_pools()
4013 return -ENOMEM; in mv_create_dma_pools()
4015 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, in mv_create_dma_pools()
4017 if (!hpriv->sg_tbl_pool) in mv_create_dma_pools()
4018 return -ENOMEM; in mv_create_dma_pools()
4029 writel(0, hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4030 writel(0, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4033 for (i = 0; i < dram->num_cs; i++) { in mv_conf_mbus_windows()
4034 const struct mbus_dram_window *cs = dram->cs + i; in mv_conf_mbus_windows()
4036 writel(((cs->size - 1) & 0xffff0000) | in mv_conf_mbus_windows()
4037 (cs->mbus_attr << 8) | in mv_conf_mbus_windows()
4038 (dram->mbus_dram_target_id << 4) | 1, in mv_conf_mbus_windows()
4039 hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4040 writel(cs->base, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4045 * mv_platform_probe - handle a positive probe of an soc Marvell
4065 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_platform_probe()
4070 if (unlikely(pdev->num_resources != 2)) { in mv_platform_probe()
4071 dev_err(&pdev->dev, "invalid number of resources\n"); in mv_platform_probe()
4072 return -EINVAL; in mv_platform_probe()
4080 return -EINVAL; in mv_platform_probe()
4083 if (pdev->dev.of_node) { in mv_platform_probe()
4084 rc = of_property_read_u32(pdev->dev.of_node, "nr-ports", in mv_platform_probe()
4087 dev_err(&pdev->dev, in mv_platform_probe()
4088 "error parsing nr-ports property: %d\n", rc); in mv_platform_probe()
4093 dev_err(&pdev->dev, "nr-ports must be positive: %d\n", in mv_platform_probe()
4095 return -EINVAL; in mv_platform_probe()
4098 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in mv_platform_probe()
4100 mv_platform_data = dev_get_platdata(&pdev->dev); in mv_platform_probe()
4101 n_ports = mv_platform_data->n_ports; in mv_platform_probe()
4107 return -EINVAL; in mv_platform_probe()
4109 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_platform_probe()
4110 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_platform_probe()
4113 return -ENOMEM; in mv_platform_probe()
4114 hpriv->port_clks = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4117 if (!hpriv->port_clks) in mv_platform_probe()
4118 return -ENOMEM; in mv_platform_probe()
4119 hpriv->port_phys = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4122 if (!hpriv->port_phys) in mv_platform_probe()
4123 return -ENOMEM; in mv_platform_probe()
4124 host->private_data = hpriv; in mv_platform_probe()
4125 hpriv->board_idx = chip_soc; in mv_platform_probe()
4127 host->iomap = NULL; in mv_platform_probe()
4128 hpriv->base = devm_ioremap(&pdev->dev, res->start, in mv_platform_probe()
4130 if (!hpriv->base) in mv_platform_probe()
4131 return -ENOMEM; in mv_platform_probe()
4133 hpriv->base -= SATAHC0_REG_BASE; in mv_platform_probe()
4135 hpriv->clk = clk_get(&pdev->dev, NULL); in mv_platform_probe()
4136 if (IS_ERR(hpriv->clk)) in mv_platform_probe()
4137 dev_notice(&pdev->dev, "cannot get optional clkdev\n"); in mv_platform_probe()
4139 clk_prepare_enable(hpriv->clk); in mv_platform_probe()
4144 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); in mv_platform_probe()
4145 if (!IS_ERR(hpriv->port_clks[port])) in mv_platform_probe()
4146 clk_prepare_enable(hpriv->port_clks[port]); in mv_platform_probe()
4149 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, in mv_platform_probe()
4151 if (IS_ERR(hpriv->port_phys[port])) { in mv_platform_probe()
4152 rc = PTR_ERR(hpriv->port_phys[port]); in mv_platform_probe()
4153 hpriv->port_phys[port] = NULL; in mv_platform_probe()
4154 if (rc != -EPROBE_DEFER) in mv_platform_probe()
4155 dev_warn(&pdev->dev, "error getting phy %d", rc); in mv_platform_probe()
4158 hpriv->n_ports = port; in mv_platform_probe()
4161 phy_power_on(hpriv->port_phys[port]); in mv_platform_probe()
4165 hpriv->n_ports = n_ports; in mv_platform_probe()
4168 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_probe()
4174 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_platform_probe()
4182 if (pdev->dev.of_node && in mv_platform_probe()
4183 of_device_is_compatible(pdev->dev.of_node, in mv_platform_probe()
4184 "marvell,armada-370-sata")) in mv_platform_probe()
4185 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; in mv_platform_probe()
4192 dev_info(&pdev->dev, "slots %u ports %d\n", in mv_platform_probe()
4193 (unsigned)MV_MAX_Q_DEPTH, host->n_ports); in mv_platform_probe()
4200 if (!IS_ERR(hpriv->clk)) { in mv_platform_probe()
4201 clk_disable_unprepare(hpriv->clk); in mv_platform_probe()
4202 clk_put(hpriv->clk); in mv_platform_probe()
4204 for (port = 0; port < hpriv->n_ports; port++) { in mv_platform_probe()
4205 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_probe()
4206 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_probe()
4207 clk_put(hpriv->port_clks[port]); in mv_platform_probe()
4209 phy_power_off(hpriv->port_phys[port]); in mv_platform_probe()
4217 * mv_platform_remove - unplug a platform interface
4226 struct mv_host_priv *hpriv = host->private_data; in mv_platform_remove()
4230 if (!IS_ERR(hpriv->clk)) { in mv_platform_remove()
4231 clk_disable_unprepare(hpriv->clk); in mv_platform_remove()
4232 clk_put(hpriv->clk); in mv_platform_remove()
4234 for (port = 0; port < host->n_ports; port++) { in mv_platform_remove()
4235 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_remove()
4236 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_remove()
4237 clk_put(hpriv->port_clks[port]); in mv_platform_remove()
4239 phy_power_off(hpriv->port_phys[port]); in mv_platform_remove()
4261 struct mv_host_priv *hpriv = host->private_data; in mv_platform_resume()
4264 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_resume()
4288 { .compatible = "marvell,armada-370-sata", },
4289 { .compatible = "marvell,orion-sata", },
4328 * mv_print_info - Dump key info to kernel log for perusal.
4338 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_print_info()
4339 struct mv_host_priv *hpriv = host->private_data; in mv_print_info()
4363 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", in mv_print_info()
4364 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, in mv_print_info()
4365 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); in mv_print_info()
4369 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4379 unsigned int board_idx = (unsigned int)ent->driver_data; in mv_pci_init_one()
4385 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_pci_init_one()
4388 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; in mv_pci_init_one()
4390 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_pci_init_one()
4391 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_pci_init_one()
4393 return -ENOMEM; in mv_pci_init_one()
4394 host->private_data = hpriv; in mv_pci_init_one()
4395 hpriv->n_ports = n_ports; in mv_pci_init_one()
4396 hpriv->board_idx = board_idx; in mv_pci_init_one()
4404 if (rc == -EBUSY) in mv_pci_init_one()
4408 host->iomap = pcim_iomap_table(pdev); in mv_pci_init_one()
4409 hpriv->base = host->iomap[MV_PRIMARY_BAR]; in mv_pci_init_one()
4411 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in mv_pci_init_one()
4413 dev_err(&pdev->dev, "DMA enable failed\n"); in mv_pci_init_one()
4417 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_pci_init_one()
4421 for (port = 0; port < host->n_ports; port++) { in mv_pci_init_one()
4422 struct ata_port *ap = host->ports[port]; in mv_pci_init_one()
4423 void __iomem *port_mmio = mv_port_base(hpriv->base, port); in mv_pci_init_one()
4424 unsigned int offset = port_mmio - hpriv->base; in mv_pci_init_one()
4426 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); in mv_pci_init_one()
4435 /* Enable message-switched interrupts, if requested */ in mv_pci_init_one()
4437 hpriv->hp_flags |= MV_HP_FLAG_MSI; in mv_pci_init_one()
4444 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, in mv_pci_init_one()
4472 int rc = -ENODEV; in mv_init()
4496 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");