Lines Matching +full:0 +full:x5b
44 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
53 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
65 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
66 { XFER_UDMA_5, 0x12446231 },
67 { XFER_UDMA_4, 0x12446231 },
68 { XFER_UDMA_3, 0x126c6231 },
69 { XFER_UDMA_2, 0x12486231 },
70 { XFER_UDMA_1, 0x124c6233 },
71 { XFER_UDMA_0, 0x12506297 },
73 { XFER_MW_DMA_2, 0x22406c31 },
74 { XFER_MW_DMA_1, 0x22406c33 },
75 { XFER_MW_DMA_0, 0x22406c97 },
77 { XFER_PIO_4, 0x06414e31 },
78 { XFER_PIO_3, 0x06414e42 },
79 { XFER_PIO_2, 0x06414e53 },
80 { XFER_PIO_1, 0x06814e93 },
81 { XFER_PIO_0, 0x06814ea7 }
85 { XFER_UDMA_6, 0x12848242 },
86 { XFER_UDMA_5, 0x12848242 },
87 { XFER_UDMA_4, 0x12ac8242 },
88 { XFER_UDMA_3, 0x128c8242 },
89 { XFER_UDMA_2, 0x120c8242 },
90 { XFER_UDMA_1, 0x12148254 },
91 { XFER_UDMA_0, 0x121882ea },
93 { XFER_MW_DMA_2, 0x22808242 },
94 { XFER_MW_DMA_1, 0x22808254 },
95 { XFER_MW_DMA_0, 0x228082ea },
97 { XFER_PIO_4, 0x0a81f442 },
98 { XFER_PIO_3, 0x0a81f443 },
99 { XFER_PIO_2, 0x0a81f454 },
100 { XFER_PIO_1, 0x0ac1f465 },
101 { XFER_PIO_0, 0x0ac1f48a }
105 { XFER_UDMA_6, 0x1c869c62 },
106 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
107 { XFER_UDMA_4, 0x1c8a9c62 },
108 { XFER_UDMA_3, 0x1c8e9c62 },
109 { XFER_UDMA_2, 0x1c929c62 },
110 { XFER_UDMA_1, 0x1c9a9c62 },
111 { XFER_UDMA_0, 0x1c829c62 },
113 { XFER_MW_DMA_2, 0x2c829c62 },
114 { XFER_MW_DMA_1, 0x2c829c66 },
115 { XFER_MW_DMA_0, 0x2c829d2e },
117 { XFER_PIO_4, 0x0c829c62 },
118 { XFER_PIO_3, 0x0c829c84 },
119 { XFER_PIO_2, 0x0c829ca6 },
120 { XFER_PIO_1, 0x0d029d26 },
121 { XFER_PIO_0, 0x0d029d5e }
221 return 0xffffffffU; /* silence compiler warning */ in hpt37x_find_mode()
233 if (i >= 0) { in hpt_dma_blacklisted()
237 return 0; in hpt_dma_blacklisted()
266 "IC35L010AVER07-0",
267 "IC35L020AVER07-0",
268 "IC35L030AVER07-0",
269 "IC35L040AVER07-0",
270 "IC35L060AVER07-0",
289 mask &= ~(0xE0 << ATA_SHIFT_UDMA); in hpt370_filter()
306 mask &= ~(0xE0 << ATA_SHIFT_UDMA); in hpt370a_filter()
322 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); in hpt372_filter()
339 pci_read_config_byte(pdev, 0x5B, &scr2); in hpt37x_cable_detect()
340 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); in hpt37x_cable_detect()
345 pci_read_config_byte(pdev, 0x5A, &ata66); in hpt37x_cable_detect()
347 pci_write_config_byte(pdev, 0x5B, scr2); in hpt37x_cable_detect()
365 unsigned int mcrbase = 0x50 + 4 * ap->port_no; in hpt374_fn1_cable_detect()
371 /* Set bit 15 of 0x52 to enable TCBLID as input */ in hpt374_fn1_cable_detect()
372 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); in hpt374_fn1_cable_detect()
373 pci_read_config_byte(pdev, 0x5A, &ata66); in hpt374_fn1_cable_detect()
396 { 0x50, 1, 0x04, 0x04 }, in hpt37x_pre_reset()
397 { 0x54, 1, 0x04, 0x04 } in hpt37x_pre_reset()
404 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); in hpt37x_pre_reset()
418 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); in hpt370_set_mode()
419 addr2 = 0x51 + 4 * ap->port_no; in hpt370_set_mode()
423 fast &= ~0x02; in hpt370_set_mode()
424 fast |= 0x01; in hpt370_set_mode()
429 mask = 0xcfc3ffff; in hpt370_set_mode()
431 mask = 0x31c001ff; in hpt370_set_mode()
433 mask = 0x303c0000; in hpt370_set_mode()
488 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); in hpt370_bmdma_stop()
498 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); in hpt370_bmdma_stop()
512 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); in hpt372_set_mode()
513 addr2 = 0x51 + 4 * ap->port_no; in hpt372_set_mode()
517 fast &= ~0x07; in hpt372_set_mode()
522 mask = 0xcfc3ffff; in hpt372_set_mode()
524 mask = 0x31c001ff; in hpt372_set_mode()
526 mask = 0x303c0000; in hpt372_set_mode()
572 int mscreg = 0x50 + 4 * ap->port_no; in hpt37x_bmdma_stop()
575 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); in hpt37x_bmdma_stop()
578 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); in hpt37x_bmdma_stop()
653 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
661 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
683 for (tries = 0; tries < 0x5000; tries++) { in hpt37x_calibrate_dpll()
685 pci_read_config_byte(dev, 0x5b, ®5b); in hpt37x_calibrate_dpll()
686 if (reg5b & 0x80) { in hpt37x_calibrate_dpll()
688 for (tries = 0; tries < 0x1000; tries++) { in hpt37x_calibrate_dpll()
689 pci_read_config_byte(dev, 0x5b, ®5b); in hpt37x_calibrate_dpll()
691 if ((reg5b & 0x80) == 0) in hpt37x_calibrate_dpll()
692 return 0; in hpt37x_calibrate_dpll()
695 pci_read_config_dword(dev, 0x5c, ®5c); in hpt37x_calibrate_dpll()
696 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); in hpt37x_calibrate_dpll()
701 return 0; in hpt37x_calibrate_dpll()
715 return 0; in hpt374_read_freq()
717 freq = inl(io_base + 0x90); in hpt374_read_freq()
720 freq = inl(io_base + 0x90); in hpt374_read_freq()
738 * HPT366 4 (HPT366) 0 Other driver
853 ppi[0] = &info_hpt370; in hpt37x_init_one()
855 prefer_dpll = 0; in hpt37x_init_one()
858 ppi[0] = &info_hpt370a; in hpt37x_init_one()
860 prefer_dpll = 0; in hpt37x_init_one()
863 ppi[0] = &info_hpt372; in hpt37x_init_one()
876 ppi[0] = &info_hpt372; in hpt37x_init_one()
883 ppi[0] = &info_hpt302; in hpt37x_init_one()
890 ppi[0] = &info_hpt302; in hpt37x_init_one()
896 pci_read_config_byte(dev, 0x50, &mcr1); in hpt37x_init_one()
897 mcr1 &= ~0x04; in hpt37x_init_one()
898 pci_write_config_byte(dev, 0x50, mcr1); in hpt37x_init_one()
914 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); in hpt37x_init_one()
915 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); in hpt37x_init_one()
916 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); in hpt37x_init_one()
918 pci_read_config_byte(dev, 0x5A, &irqmask); in hpt37x_init_one()
919 irqmask &= ~0x10; in hpt37x_init_one()
920 pci_write_config_byte(dev, 0x5a, irqmask); in hpt37x_init_one()
929 pci_write_config_byte(dev, 0x5b, 0x23); in hpt37x_init_one()
936 outb(0x0e, iobase + 0x9c); in hpt37x_init_one()
941 * from FN 0 on the HPT374. in hpt37x_init_one()
946 if (freq == 0) in hpt37x_init_one()
949 freq = inl(iobase + 0x90); in hpt37x_init_one()
951 if ((freq >> 12) != 0xABCDE) { in hpt37x_init_one()
954 u32 total = 0; in hpt37x_init_one()
959 for (i = 0; i < 128; i++) { in hpt37x_init_one()
960 pci_read_config_byte(dev, 0x78, &sr); in hpt37x_init_one()
961 total += sr & 0x1FF; in hpt37x_init_one()
966 freq &= 0x1FF; in hpt37x_init_one()
985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
993 pci_write_config_byte(dev, 0x5b, 0x21); in hpt37x_init_one()
994 pci_write_config_dword(dev, 0x5C, in hpt37x_init_one()
995 (f_high << 16) | f_low | 0x100); in hpt37x_init_one()
997 for (adjust = 0; adjust < 8; adjust++) { in hpt37x_init_one()
1008 pci_write_config_dword(dev, 0x5C, in hpt37x_init_one()
1009 (f_high << 16) | f_low | 0x100); in hpt37x_init_one()
1030 if (clock_slot < 2 && ppi[0] == &info_hpt370) in hpt37x_init_one()
1031 ppi[0] = &info_hpt370_33; in hpt37x_init_one()
1032 if (clock_slot < 2 && ppi[0] == &info_hpt370a) in hpt37x_init_one()
1033 ppi[0] = &info_hpt370a_33; in hpt37x_init_one()
1040 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); in hpt37x_init_one()