31 #define SCFG_OFFSET					0x1000  macro
208 	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra124_ahci_init()
211 		    SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);  in tegra124_ahci_init()
216 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra124_ahci_init()
220 		    SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);  in tegra124_ahci_init()
225 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra124_ahci_init()
229 	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);  in tegra124_ahci_init()
231 	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);  in tegra124_ahci_init()
233 	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra124_ahci_init()
326 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);  in tegra_ahci_controller_init()
328 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);  in tegra_ahci_controller_init()
330 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);  in tegra_ahci_controller_init()
332 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);  in tegra_ahci_controller_init()
336 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);  in tegra_ahci_controller_init()
339 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);  in tegra_ahci_controller_init()
341 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);  in tegra_ahci_controller_init()
348 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);  in tegra_ahci_controller_init()
353 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);  in tegra_ahci_controller_init()
356 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);  in tegra_ahci_controller_init()
365 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
368 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
370 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);  in tegra_ahci_controller_init()
373 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
375 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
377 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);  in tegra_ahci_controller_init()
382 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);  in tegra_ahci_controller_init()
384 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
386 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
389 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);  in tegra_ahci_controller_init()
394 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);  in tegra_ahci_controller_init()
400 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);  in tegra_ahci_controller_init()
403 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);  in tegra_ahci_controller_init()
406 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);  in tegra_ahci_controller_init()
408 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);  in tegra_ahci_controller_init()
411 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);  in tegra_ahci_controller_init()