Lines Matching +full:way +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_BINFMT_FLAT if !MMU
6 select ARCH_HAS_DMA_PREP_COHERENT if MMU
7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
9 select ARCH_HAS_DMA_SET_UNCACHED if MMU
10 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN
11 select ARCH_HAS_STRNLEN_USER
12 select ARCH_USE_MEMTEST
13 select ARCH_USE_QUEUED_RWLOCKS
14 select ARCH_USE_QUEUED_SPINLOCKS
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_WANT_IPC_PARSE_VERSION
17 select BUILDTIME_TABLE_SORT
18 select CLONE_BACKWARDS
19 select COMMON_CLK
20 select DMA_REMAP if MMU
21 select GENERIC_ATOMIC64
22 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP
24 select GENERIC_SCHED_CLOCK
25 select HAVE_ARCH_AUDITSYSCALL
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER
29 select HAVE_ARCH_TRACEHOOK
30 select HAVE_DEBUG_KMEMLEAK
31 select HAVE_DMA_CONTIGUOUS
32 select HAVE_EXIT_THREAD
33 select HAVE_FUNCTION_TRACER
34 select HAVE_FUTEX_CMPXCHG if !MMU && FUTEX
35 select HAVE_HW_BREAKPOINT if PERF_EVENTS
36 select HAVE_IRQ_TIME_ACCOUNTING
37 select HAVE_PCI
38 select HAVE_PERF_EVENTS
39 select HAVE_STACKPROTECTOR
40 select HAVE_SYSCALL_TRACEPOINTS
41 select IRQ_DOMAIN
42 select MODULES_USE_ELF_RELA
43 select PERF_USE_VMALLOC
44 select SET_FS
45 select TRACE_IRQFLAGS_SUPPORT
46 select VIRT_TO_BUS
48 Xtensa processors are 32-bit RISC machines designed by Tensilica
53 a home page at <http://www.linux-xtensa.org/>.
88 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
100 bool "fsf - default (not generic) configuration"
101 select MMU
104 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
105 select MMU
106 select HAVE_XTENSA_GPIO32
111 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
112 select MMU
113 select HAVE_XTENSA_GPIO32
119 select HAVE_XTENSA_GPIO32
121 Select this variant to use a custom Xtensa processor configuration.
131 Don't forget you have to select MMU if you have one.
144 select MMU
147 ie: it supports a TLB with auto-loading, page protection.
187 select XTENSA_MX
189 This option is used to indicate that the system-on-a-chip (SOC)
200 You still have to select "Enable SMP" to enable SMP on this SOC.
203 bool "Enable Symmetric multi-processing support"
205 select GENERIC_SMP_IDLE_THREAD
212 int "Maximum number of CPUs (2-32)"
258 Select supported userspace ABI.
271 select USER_ABI_CALL0
273 Select this option to support only call0 ABI in userspace.
282 select USER_ABI_CALL0
284 Select this option to support both windowed and call0 userspace
322 select XTENSA_CALIBRATE_CCOUNT
323 select SERIAL_CONSOLE
330 XT2000 is the name of Tensilica's feature-rich emulation platform.
335 select ETHOC if ETHERNET
336 select PLATFORM_WANT_DEFAULT_MEM if !MMU
337 select SERIAL_CONSOLE
338 select XTENSA_CALIBRATE_CCOUNT
339 select PLATFORM_HAVE_XIP
369 On some architectures (EBSA110 and CATS), there is currently no way
371 architectures, you should supply some command-line options at build
377 select OF
378 select OF_EARLY_FLATTREE
418 tristate "Host file-based simulated block device support"
427 int "Number of host file-based simulated block devices"
450 Another simulated disk in a host file for a buildroot-independent
475 bool "Use 8-bit access to XTFPGA LCD"
479 LCD may be connected with 4- or 8-bit interface, 8-bit access may
480 only be used with 8-bit interface. Please consult prototyping user
496 This unfortunately won't work for U-Boot and likely also won't
502 xt-gdb can't place a Software Breakpoint in the 0XD region prior
510 Selecting this will cause U-Boot to set the KERNEL Load and Entry
516 bool "Kernel Execute-In-Place from ROM"
519 Execute-In-Place allows the kernel to run from non-volatile storage
522 to RAM. Read-write sections, such as the data section and stack,
543 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
544 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
563 2: WB, no-write-allocate cache,
609 placed at their hardware-defined locations.
626 XIP-aware MTD support.
668 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
677 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
685 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
694 select KMAP_LOCAL