1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/nospec-branch.h>
34  *	TLB flushing, formerly SMP-only
65  * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
72  * ASID  - [0, TLB_NR_DYN_ASIDS-1]
75  * kPCID - [1, TLB_NR_DYN_ASIDS]
79  * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
99 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
102  * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
103  * for them being zero-based.  Another -1 is because PCID 0 is reserved for
104  * use by non-PCID-aware users.
106 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
129 	 * The dynamically-assigned ASIDs that get passed in are small  in kern_pcid()
133 	 * If PCID is on, ASID-aware code paths put the ASID+1 into the  in kern_pcid()
135 	 * situation in which PCID-unaware code saves CR3, loads some other  in kern_pcid()
137 	 * the TLB for ASID 0 if the saved ASID was nonzero.  It also means  in kern_pcid()
138 	 * that any bugs involving loading a PCID-enabled CR3 with  in kern_pcid()
179  * We get here when we do something requiring a TLB invalidation
182  * forces a TLB flush when the context is loaded.
229 		    next->context.ctx_id)  in choose_new_asid()
242 	*new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;  in choose_new_asid()
289 	 * that load_cr3() is serializing and orders TLB  in load_new_mm_cr3()
300 	 * It's plausible that we're in lazy TLB mode while our mm is init_mm.  in leave_mm()
301 	 * If so, our callers still expect us to flush the TLB, but there  in leave_mm()
302 	 * aren't any user TLB entries in init_mm to worry about.  in leave_mm()
328  * Invoked from return to user/guest by a task that opted-in to L1D
356 		clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH);  in l1d_flush_evaluate()
357 		next->l1d_flush_kill.func = l1d_flush_force_sigbus;  in l1d_flush_evaluate()
358 		task_work_add(next, &next->l1d_flush_kill, TWA_RESUME);  in l1d_flush_evaluate()
364 	unsigned long next_tif = task_thread_info(next)->flags;  in mm_mangle_tif_spec_bits()
373 	return (unsigned long)next->mm | spec_bits;  in mm_mangle_tif_spec_bits()
380 	if (!next || !next->mm)  in cond_mitigation()
389 	 * doing Spectre-v2 attacks on another.  in cond_mitigation()
393 	 * same process. Using the mm pointer instead of mm->context.ctx_id  in cond_mitigation()
416 		 * - the same user space task is scheduled out and later  in cond_mitigation()
420 		 * - a user space task belonging to the same process is  in cond_mitigation()
423 		 * - a user space task belonging to the same process is  in cond_mitigation()
446 					(unsigned long)next->mm)  in cond_mitigation()
468 	     atomic_read(&mm->context.perf_rdpmc_allowed))) {  in cr4_update_pce_mm()
501 	 * from lazy TLB mode to normal mode if active_mm isn't changing.  in switch_mm_irqs_off()
522 	if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {  in switch_mm_irqs_off()
524 		 * If we were to BUG here, we'd be very likely to kill  in switch_mm_irqs_off()
543 	 * core serialization before returning to user-space, after  in switch_mm_irqs_off()
544 	 * storing to rq->curr, when changing mm.  This is because  in switch_mm_irqs_off()
555 			   next->context.ctx_id);  in switch_mm_irqs_off()
558 		 * Even in lazy TLB mode, the CPU should stay set in the  in switch_mm_irqs_off()
559 		 * mm_cpumask. The TLB shootdown code can figure out from  in switch_mm_irqs_off()
567 		 * If the CPU is not in lazy TLB mode, we are just switching  in switch_mm_irqs_off()
569 		 * process. No TLB flush required.  in switch_mm_irqs_off()
576 		 * If the TLB is up to date, just use it.  in switch_mm_irqs_off()
578 		 * the TLB shootdown code.  in switch_mm_irqs_off()
581 		next_tlb_gen = atomic64_read(&next->context.tlb_gen);  in switch_mm_irqs_off()
587 		 * TLB contents went out of date while we were in lazy  in switch_mm_irqs_off()
588 		 * mode. Fall through to the TLB switching code below.  in switch_mm_irqs_off()
601 		 * Skip kernel threads; we never send init_mm TLB flushing IPIs,  in switch_mm_irqs_off()
615 		next_tlb_gen = atomic64_read(&next->context.tlb_gen);  in switch_mm_irqs_off()
625 		this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);  in switch_mm_irqs_off()
627 		load_new_mm_cr3(next->pgd, new_asid, true);  in switch_mm_irqs_off()
632 		load_new_mm_cr3(next->pgd, new_asid, false);  in switch_mm_irqs_off()
656  * lazy tricks to try to minimize TLB flushes.
674  * - The ASID changed from what cpu_tlbstate thinks it is (most likely
678  * - The TLB contains junk in slots corresponding to inactive ASIDs.
680  * - The CPU went so far out to lunch that it may have missed a TLB
691 	WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));  in initialize_tlbstate_and_flush()
701 	/* Force ASID 0 and force a TLB flush. */  in initialize_tlbstate_and_flush()
702 	write_cr3(build_cr3(mm->pgd, 0));  in initialize_tlbstate_and_flush()
708 	this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);  in initialize_tlbstate_and_flush()
717  * TLB fills that happen after we flush the TLB are ordered after we
727 	 * - mm_tlb_gen:     the latest generation.  in flush_tlb_func()
728 	 * - local_tlb_gen:  the generation that this CPU has already caught  in flush_tlb_func()
730 	 * - f->new_tlb_gen: the generation that the requester of the flush  in flush_tlb_func()
736 	u64 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);  in flush_tlb_func()
738 	bool local = smp_processor_id() == f->initiating_cpu;  in flush_tlb_func()
749 		if (f->mm && f->mm != loaded_mm)  in flush_tlb_func()
757 		   loaded_mm->context.ctx_id);  in flush_tlb_func()
762 		 * paging-structure cache to avoid speculatively reading  in flush_tlb_func()
763 		 * garbage into our TLB.  Since switching to init_mm is barely  in flush_tlb_func()
767 		 * IPIs to lazy TLB mode CPUs.  in flush_tlb_func()
776 		 * happen if two concurrent flushes happen -- the first flush to  in flush_tlb_func()
784 	WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);  in flush_tlb_func()
787 	 * If we get to this point, we know that our TLB is out of date.  in flush_tlb_func()
789 	 * possible that f->new_tlb_gen <= local_tlb_gen), but we're  in flush_tlb_func()
798 	 * 1. f->new_tlb_gen == local_tlb_gen + 1.  We have an invariant that  in flush_tlb_func()
801 	 *    f->new_tlb_gen == 3, then we know that the flush needed to bring  in flush_tlb_func()
812 	 *    3, we'd be break the invariant: we'd update local_tlb_gen above  in flush_tlb_func()
815 	 * 2. f->new_tlb_gen == mm_tlb_gen.  This is purely an optimization.  in flush_tlb_func()
816 	 *    Partial TLB flushes are not all that much cheaper than full TLB  in flush_tlb_func()
818 	 *    to do a partial flush if that won't bring our TLB fully up to  in flush_tlb_func()
823 	if (f->end != TLB_FLUSH_ALL &&  in flush_tlb_func()
824 	    f->new_tlb_gen == local_tlb_gen + 1 &&  in flush_tlb_func()
825 	    f->new_tlb_gen == mm_tlb_gen) {  in flush_tlb_func()
827 		unsigned long addr = f->start;  in flush_tlb_func()
829 		nr_invalidate = (f->end - f->start) >> f->stride_shift;  in flush_tlb_func()
831 		while (addr < f->end) {  in flush_tlb_func()
833 			addr += 1UL << f->stride_shift;  in flush_tlb_func()
852 				(f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN :  in flush_tlb_func()
872 	 * cases in which a remote TLB flush will be traced, but eventually  in native_flush_tlb_multi()
876 	if (info->end == TLB_FLUSH_ALL)  in native_flush_tlb_multi()
880 				(info->end - info->start) >> PAGE_SHIFT);  in native_flush_tlb_multi()
884 	 * CPUs in lazy TLB mode. They will flush the CPU themselves  in native_flush_tlb_multi()
888 	 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping  in native_flush_tlb_multi()
892 	if (info->freed_tables) {  in native_flush_tlb_multi()
897 		 * open-coding it has performance advantages, as it eliminates  in native_flush_tlb_multi()
903 		 * TLB flushes, an assumption that is already made in  in native_flush_tlb_multi()
906 		 * cond_cpumask is logically a stack-local variable, but it is  in native_flush_tlb_multi()
909 		 * non-reentrant.  in native_flush_tlb_multi()
931  * See Documentation/x86/tlb.rst for details.  We choose 33
957 	 * Ensure that the following code is non-reentrant and flush_tlb_info  in get_flush_tlb_info()
958 	 * is not overwritten. This means no TLB flushing is initiated by  in get_flush_tlb_info()
959 	 * interrupt handlers and machine-check exception handlers.  in get_flush_tlb_info()
964 	info->start		= start;  in get_flush_tlb_info()
965 	info->end		= end;  in get_flush_tlb_info()
966 	info->mm		= mm;  in get_flush_tlb_info()
967 	info->stride_shift	= stride_shift;  in get_flush_tlb_info()
968 	info->freed_tables	= freed_tables;  in get_flush_tlb_info()
969 	info->new_tlb_gen	= new_tlb_gen;  in get_flush_tlb_info()
970 	info->initiating_cpu	= smp_processor_id();  in get_flush_tlb_info()
996 	    ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {  in flush_tlb_mm_range()
1009 	 * a local TLB flush is needed. Optimize this use-case by calling  in flush_tlb_mm_range()
1044 	for (addr = f->start; addr < f->end; addr += PAGE_SIZE)  in do_kernel_range_flush()
1052 	    (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {  in flush_tlb_kernel_range()
1076 	unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,  in __get_current_cr3_fast()
1100 	 * If PTI is on, then the kernel is mapped with non-global PTEs, and  in flush_tlb_one_kernel()
1165 	 * Read-modify-write to CR4 - protect it from preemption and  in native_flush_tlb_global()
1194 	/* If current->mm == NULL then the read_cr3() "borrows" an mm */  in native_flush_tlb_local()
1218 		 * !PGE -> !PCID (setup_pcid()), thus every flush is total.  in __flush_tlb_all()
1234 	 * a local TLB flush is needed. Optimize this use-case by calling  in arch_tlbbatch_flush()
1237 	if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {  in arch_tlbbatch_flush()
1238 		flush_tlb_multi(&batch->cpumask, info);  in arch_tlbbatch_flush()
1239 	} else if (cpumask_test_cpu(cpu, &batch->cpumask)) {  in arch_tlbbatch_flush()
1246 	cpumask_clear(&batch->cpumask);  in arch_tlbbatch_flush()
1262 	struct mm_struct *current_mm = current->mm;  in nmi_uaccess_okay()
1268 	 * current_mm->pgd == __va(read_cr3_pa()).  This may be slow, though,  in nmi_uaccess_okay()
1274 	 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.  in nmi_uaccess_okay()
1279 	VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));  in nmi_uaccess_okay()
1301 	len = min(count, sizeof(buf) - 1);  in tlbflush_write_file()
1303 		return -EFAULT;  in tlbflush_write_file()
1307 		return -EINVAL;  in tlbflush_write_file()
1310 		return -EINVAL;  in tlbflush_write_file()