33 unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
42  * TSC can be unstable due to cpufreq or due to unsynced TSCs
228 	 * Fall back to jiffies if there's no TSC available:  in native_sched_clock()
229 	 * ( But note that we still use it if the TSC is marked  in native_sched_clock()
241  * Generate a sched_clock if you already have a TSC value.
243 u64 native_sched_clock_from_tsc(u64 tsc)  in native_sched_clock_from_tsc()  argument
245 	return cycles_2_ns(tsc);  in native_sched_clock_from_tsc()
281  * disable flag for tsc. Takes effect by clearing the TSC cpu flag
309 __setup("tsc=", tsc_setup);
315  * Read TSC and the reference counters. Take care of any disturbances
337  * Calculate the TSC frequency from HPET reference
354  * Calculate the TSC frequency from PMTimer reference
383  * Try to calibrate the TSC against the Programmable
384  * Interrupt Timer and return the frequency of the TSC
391 	u64 tsc, t1, t2, delta;  in pit_calibrate_tsc()  local
421 	tsc = t1 = t2 = get_cycles();  in pit_calibrate_tsc()
428 		delta = t2 - tsc;  in pit_calibrate_tsc()
429 		tsc = t2;  in pit_calibrate_tsc()
471  *    see the same MSB (and overhead like doing a single TSC
487  * use the TSC value at the transitions to calculate a pretty
488  * good value for the TSC frequency.
500 	u64 tsc = 0, prev_tsc = 0;  in pit_expect_msb()  local
505 		prev_tsc = tsc;  in pit_expect_msb()
506 		tsc = get_cycles();  in pit_expect_msb()
509 	*tscp = tsc;  in pit_expect_msb()
513 	 * will be based on the error terms on the TSC values.  in pit_expect_msb()
530 	u64 tsc, delta;  in quick_pit_calibrate()  local
562 	if (pit_expect_msb(0xff, &tsc, &d1)) {  in quick_pit_calibrate()
567 			delta -= tsc;  in quick_pit_calibrate()
585 			 * all TSC reads were stable wrt the PIT.  in quick_pit_calibrate()
595 	pr_info("Fast TSC calibration failed\n");  in quick_pit_calibrate()
605 	 * any odd delays anywhere, and the TSC reads are  in quick_pit_calibrate()
614 	pr_info("Fast TSC calibration using PIT\n");  in quick_pit_calibrate()
620  * Determine TSC frequency via CPUID, else return 0.
635 	/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */  in native_calibrate_tsc()
653 	 * TSC frequency reported directly by CPUID is a "hardware reported"  in native_calibrate_tsc()
677 	 * For Atom SoCs TSC is the only reliable clocksource.  in native_calibrate_tsc()
678 	 * Mark TSC reliable so no watchdog on it.  in native_calibrate_tsc()
732 	 * zero. In each wait loop iteration we read the TSC and check  in pit_hpet_ptimer_calibrate_cpu()
742 	 * We use separate TSC readouts and check inside of the  in pit_hpet_ptimer_calibrate_cpu()
769 		/* Pick the lowest PIT TSC calibration so far */  in pit_hpet_ptimer_calibrate_cpu()
824 		/* We don't have an alternative source, disable TSC */  in pit_hpet_ptimer_calibrate_cpu()
830 		/* The alternative source failed as well, disable TSC */  in pit_hpet_ptimer_calibrate_cpu()
930  * Even on processors with invariant TSC, TSC gets reset in some the
931  * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
969  * Frequency scaling support. Adjust the TSC based timer when the CPU frequency
972  * NOTE: On SMP the situation is not fixable in general, so simply mark the TSC
1038  * If ART is present detect the numerator:denominator to convert to TSC
1048 	 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,  in detect_art()
1049 	 * and the TSC counter resets must not occur asynchronously.  in detect_art()
1078  * We used to compare the TSC to the cycle_last value in the clocksource
1081  * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1082  * is smaller than the cycle_last reference value due to a TSC which
1107 	pr_info("Marking TSC unstable due to clocksource watchdog\n");  in tsc_cs_mark_unstable()
1129 	.name			= "tsc-early",
1146  * this one will immediately take over. We will only register if TSC has
1150 	.name			= "tsc",
1175 	pr_info("Marking TSC unstable due to %s\n", reason);  in mark_tsc_unstable()
1192 		/* Geode_LX - the OLPC CPU has a very reliable TSC */  in check_system_tsc_reliable()
1202  * Make an educated guess if the TSC is trustworthy and synchronized
1222 	 * Exceptions must mark TSC as unstable:  in unsynchronized_tsc()
1234  * Convert ART to TSC given numerator/denominator found in detect_art()
1254  * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
1259  * to TSC.
1263  * that this flag is set before conversion to TSC is attempted.
1295  * tsc_refine_calibration_work - Further refine tsc freq calibration
1299  * second to further refine the TSC freq value. Since this is
1316 	/* Don't bother refining TSC on unstable systems */  in tsc_refine_calibration_work()
1359 	pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",  in tsc_refine_calibration_work()
1363 	/* Inform the TSC deadline clockevent devices about the recalibration */  in tsc_refine_calibration_work()
1397 	 * When TSC frequency is known (retrieved via MSR or CPUID), we skip  in init_tsc_clocksource()
1420 	/* Make sure that cpu and tsc are not already calibrated */  in determine_cpu_tsc_frequencies()
1453 		pr_info("Detected %lu.%03lu MHz TSC",  in determine_cpu_tsc_frequencies()
1470 	/* Sanitize TSC ADJUST before cyc2ns gets initialized */  in tsc_enable_sched_clock()
1480 	/* Don't change UV TSC multi-chassis synchronization */  in tsc_early_init()
1507 			mark_tsc_unstable("could not calculate TSC khz");  in tsc_init()
1538  * If we have a constant TSC and are using the TSC for the delay loop,