1 // SPDX-License-Identifier: GPL-2.0+
15 #include <asm/spec-ctrl.h>
23  * nodes_per_socket: Stores the number of nodes per socket.
37 	for (i = apicid - 1; i >= 0; i--) {  in nearby_node()
59  * (1) Hygon multi-node processors
67 	/* get information required for multi-node processors */  in hygon_get_topology()
74 		c->cpu_die_id  = ecx & 0xff;  in hygon_get_topology()
76 		c->cpu_core_id = ebx & 0xff;  in hygon_get_topology()
79 			c->x86_max_cores /= smp_num_siblings;  in hygon_get_topology()
87 			c->x86_coreid_bits = get_count_order(c->x86_max_cores);  in hygon_get_topology()
89 		/* Socket ID is ApicId[6] for these processors. */  in hygon_get_topology()
90 		c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;  in hygon_get_topology()
97 		c->cpu_die_id = value & 7;  in hygon_get_topology()
99 		per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;  in hygon_get_topology()
116 	bits = c->x86_coreid_bits;  in hygon_detect_cmp()
117 	/* Low order bits define the core id (index of core in socket) */  in hygon_detect_cmp()
118 	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);  in hygon_detect_cmp()
119 	/* Convert the initial APIC ID into the socket ID */  in hygon_detect_cmp()
120 	c->phys_proc_id = c->initial_apicid >> bits;  in hygon_detect_cmp()
121 	/* use socket ID also for last level cache */  in hygon_detect_cmp()
122 	per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;  in hygon_detect_cmp()
130 	unsigned int apicid = c->apicid;  in srat_detect_node()
137 	 * On multi-fabric platform (e.g. Numascale NumaChip) a  in srat_detect_node()
138 	 * platform-specific handler needs to be called to fixup some  in srat_detect_node()
148 		 * - The CPU is missing memory and no node was created.  In  in srat_detect_node()
151 		 * - The APIC IDs differ from the HyperTransport node IDs.  in srat_detect_node()
163 		int ht_nodeid = c->initial_apicid;  in srat_detect_node()
180 	/* Multi core CPU? */  in early_init_hygon_mc()
181 	if (c->extended_cpuid_level < 0x80000008)  in early_init_hygon_mc()
186 	c->x86_max_cores = (ecx & 0xff) + 1;  in early_init_hygon_mc()
193 		while ((1 << bits) < c->x86_max_cores)  in early_init_hygon_mc()
197 	c->x86_coreid_bits = bits;  in early_init_hygon_mc()
248 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);  in early_init_hygon()
251 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_hygon()
252 	 * with P/T states and does not stop in deep C-states  in early_init_hygon()
254 	if (c->x86_power & (1 << 8)) {  in early_init_hygon()
260 	if (c->x86_power & BIT(12))  in early_init_hygon()
264 	if (c->x86_power & BIT(14))  in early_init_hygon()
273 	 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we  in early_init_hygon()
303 	c->apicid = hard_smp_processor_id();  in init_hygon()
345 	if (c->extended_cpuid_level < 0x80000006)  in cpu_detect_tlb_hygon()